src/gallium/drivers/r600/radeon_video.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include "util/u_memory.h"
  37 #include "util/u_video.h"
  38
  39 #include "vl/vl_defines.h"
  40 #include "vl/vl_video_buffer.h"
  41
  42 #include "r600_pipe_common.h"
  43 #include "radeon_video.h"
  44 #include "radeon_vce.h"
  45
  46 #define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
  47
  48 /* generate an stream handle */
  49 unsigned rvid_alloc_stream_handle()
  50 {
  51         static unsigned counter = 0;
  52         unsigned stream_handle = 0;
  53         unsigned pid = getpid();
  54         int i;
  55
  56         for (i = 0; i < 32; ++i)
  57                 stream_handle |= ((pid >> i) & 1) << (31 - i);
  58
  59         stream_handle ^= ++counter;
  60         return stream_handle;
  61 }
  62
  63 /* create a buffer in the winsys */
  64 bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
  65                         unsigned size, unsigned usage)
  66 {
  67         memset(buffer, 0, sizeof(*buffer));
  68         buffer->usage = usage;
  69
  70         /* Hardware buffer placement restrictions require the kernel to be
  71          * able to move buffers around individually, so request a
  72          * non-sub-allocated buffer.
  73          */
  74         buffer->res = (struct r600_resource *)
  75                 pipe_buffer_create(screen, PIPE_BIND_SHARED,
  76                                    usage, size);
  77
  78         return buffer->res != NULL;
  79 }
  80
  81 /* destroy a buffer */
  82 void rvid_destroy_buffer(struct rvid_buffer *buffer)
  83 {
  84         r600_resource_reference(&buffer->res, NULL);
  85 }
  86
  87 /* reallocate a buffer, preserving its content */
  88 bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
  89                         struct rvid_buffer *new_buf, unsigned new_size)
  90 {
  91         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
  92         struct radeon_winsys* ws = rscreen->ws;
  93         unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
  94         struct rvid_buffer old_buf = *new_buf;
  95         void *src = NULL, *dst = NULL;
  96
  97         if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage))
  98                 goto error;
  99
 100         src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
 101         if (!src)
 102                 goto error;
 103
 104         dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
 105         if (!dst)
 106                 goto error;
 107
 108         memcpy(dst, src, bytes);
 109         if (new_size > bytes) {
 110                 new_size -= bytes;
 111                 dst += bytes;
 112                 memset(dst, 0, new_size);
 113         }
 114         ws->buffer_unmap(new_buf->res->buf);
 115         ws->buffer_unmap(old_buf.res->buf);
 116         rvid_destroy_buffer(&old_buf);
 117         return true;
 118
 119 error:
 120         if (src)
 121                 ws->buffer_unmap(old_buf.res->buf);
 122         rvid_destroy_buffer(new_buf);
 123         *new_buf = old_buf;
 124         return false;
 125 }
 126
 127 /* clear the buffer with zeros */
 128 void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 129 {
 130         struct r600_common_context *rctx = (struct r600_common_context*)context;
 131
 132         rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
 133                                buffer->res->buf->size, 0);
 134         context->flush(context, NULL, 0);
 135 }
 136
 137 /**
 138  * join surfaces into the same buffer with identical tiling params
 139  * sumup their sizes and replace the backend buffers with a single bo
 140  */
 141 void rvid_join_surfaces(struct r600_common_context *rctx,
 142                         struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 143                         struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 144 {
 145         struct radeon_winsys* ws;
 146         unsigned best_tiling, best_wh, off;
 147         unsigned size, alignment;
 148         struct pb_buffer *pb;
 149         unsigned i, j;
 150
 151         ws = rctx->ws;
 152
 153         for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 154                 unsigned wh;
 155
 156                 if (!surfaces[i])
 157                         continue;
 158
 159                 if (rctx->chip_class < GFX9) {
 160                         /* choose the smallest bank w/h for now */
 161                         wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
 162                         if (wh < best_wh) {
 163                                 best_wh = wh;
 164                                 best_tiling = i;
 165                         }
 166                 }
 167         }
 168
 169         for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
 170                 if (!surfaces[i])
 171                         continue;
 172
 173                 /* adjust the texture layer offsets */
 174                 off = align(off, surfaces[i]->surf_alignment);
 175
 176                 if (rctx->chip_class < GFX9) {
 177                         /* copy the tiling parameters */
 178                         surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
 179                         surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
 180                         surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
 181                         surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
 182
 183                         for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
 184                                 surfaces[i]->u.legacy.level[j].offset += off;
 185                 } else
 186                         surfaces[i]->u.gfx9.surf_offset += off;
 187
 188                 off += surfaces[i]->surf_size;
 189         }
 190
 191         for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
 192                 if (!buffers[i] || !*buffers[i])
 193                         continue;
 194
 195                 size = align(size, (*buffers[i])->alignment);
 196                 size += (*buffers[i])->size;
 197                 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
 198         }
 199
 200         if (!size)
 201                 return;
 202
 203         /* TODO: 2D tiling workaround */
 204         alignment *= 2;
 205
 206         pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
 207                                RADEON_FLAG_GTT_WC);
 208         if (!pb)
 209                 return;
 210
 211         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 212                 if (!buffers[i] || !*buffers[i])
 213                         continue;
 214
 215                 pb_reference(buffers[i], pb);
 216         }
 217
 218         pb_reference(&pb, NULL);
 219 }
 220
 221 int rvid_get_video_param(struct pipe_screen *screen,
 222                          enum pipe_video_profile profile,
 223                          enum pipe_video_entrypoint entrypoint,
 224                          enum pipe_video_cap param)
 225 {
 226         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 227         enum pipe_video_format codec = u_reduce_video_profile(profile);
 228         struct radeon_info info;
 229
 230         rscreen->ws->query_info(rscreen->ws, &info);
 231
 232         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 233                 switch (param) {
 234                 case PIPE_VIDEO_CAP_SUPPORTED:
 235                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 236                                 rvce_is_fw_version_supported(rscreen);
 237                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 238                         return 1;
 239                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 240                         return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 241                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 242                         return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
 243                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 244                         return PIPE_FORMAT_NV12;
 245                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 246                         return false;
 247                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 248                         return false;
 249                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 250                         return true;
 251                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 252                         return (rscreen->family < CHIP_TONGA) ? 1 : 2;
 253                 default:
 254                         return 0;
 255                 }
 256         }
 257
 258         switch (param) {
 259         case PIPE_VIDEO_CAP_SUPPORTED:
 260                 switch (codec) {
 261                 case PIPE_VIDEO_FORMAT_MPEG12:
 262                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 263                 case PIPE_VIDEO_FORMAT_MPEG4:
 264                         /* no support for MPEG4 on older hw */
 265                         return rscreen->family >= CHIP_PALM;
 266                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 267                         if ((rscreen->family == CHIP_POLARIS10 ||
 268                              rscreen->family == CHIP_POLARIS11) &&
 269                             info.uvd_fw_version < UVD_FW_1_66_16 ) {
 270                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 271                                 return false;
 272                         }
 273                         return true;
 274                 case PIPE_VIDEO_FORMAT_VC1:
 275                         return true;
 276                 case PIPE_VIDEO_FORMAT_HEVC:
 277                         /* Carrizo only supports HEVC Main */
 278                         if (rscreen->family >= CHIP_STONEY)
 279                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 280                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 281                         else if (rscreen->family >= CHIP_CARRIZO)
 282                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 283                         return false;
 284                 case PIPE_VIDEO_FORMAT_JPEG:
 285                         if (rscreen->family < CHIP_CARRIZO || rscreen->family >= CHIP_VEGA10)
 286                                 return false;
 287                         if (!(rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 19)) {
 288                                 RVID_ERR("No MJPEG support for the kernel version\n");
 289                                 return false;
 290                         }
 291                         return true;
 292                 default:
 293                         return false;
 294                 }
 295         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 296                 return 1;
 297         case PIPE_VIDEO_CAP_MAX_WIDTH:
 298                 return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 299         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 300                 return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
 301         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 302                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 303                         return PIPE_FORMAT_P016;
 304                 else
 305                         return PIPE_FORMAT_NV12;
 306
 307         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 308         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 309                 if (rscreen->family < CHIP_PALM) {
 310                         /* MPEG2 only with shaders and no support for
 311                            interlacing on R6xx style UVD */
 312                         return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
 313                                rscreen->family > CHIP_RV770;
 314                 } else {
 315                         enum pipe_video_format format = u_reduce_video_profile(profile);
 316
 317                         if (format == PIPE_VIDEO_FORMAT_HEVC)
 318                                 return false; //The firmware doesn't support interlaced HEVC.
 319                         else if (format == PIPE_VIDEO_FORMAT_JPEG)
 320                                 return false;
 321                         return true;
 322                 }
 323         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 324                 return true;
 325         case PIPE_VIDEO_CAP_MAX_LEVEL:
 326                 switch (profile) {
 327                 case PIPE_VIDEO_PROFILE_MPEG1:
 328                         return 0;
 329                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 330                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 331                         return 3;
 332                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 333                         return 3;
 334                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 335                         return 5;
 336                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 337                         return 1;
 338                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 339                         return 2;
 340                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 341                         return 4;
 342                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 343                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 344                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 345                         return (rscreen->family < CHIP_TONGA) ? 41 : 52;
 346                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 347                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 348                         return 186;
 349                 default:
 350                         return 0;
 351                 }
 352         default:
 353                 return 0;
 354         }
 355 }
 356
 357 boolean rvid_is_format_supported(struct pipe_screen *screen,
 358                                  enum pipe_format format,
 359                                  enum pipe_video_profile profile,
 360                                  enum pipe_video_entrypoint entrypoint)
 361 {
 362         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 363         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 364                 return (format == PIPE_FORMAT_NV12) ||
 365                         (format == PIPE_FORMAT_P016);
 366
 367         /* we can only handle this one with UVD */
 368         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 369                 return format == PIPE_FORMAT_NV12;
 370
 371         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 372 }