projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600/shader: only emit add instruction if param has a value.
[mesa.git] / src / gallium / drivers / r600 / sb / sb_sched.cpp
1 /*
2 * Copyright 2013 Vadim Girlin <vadimgirlin@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vadim Girlin
25 */
26
27 #define PSC_DEBUG 0
28
29 #if PSC_DEBUG
30 #define PSC_DUMP(a) do { a } while (0)
31 #else
32 #define PSC_DUMP(a)
33 #endif
34
35 #include "sb_bc.h"
36 #include "sb_shader.h"
37 #include "sb_pass.h"
38 #include "sb_sched.h"
39 #include "eg_sq.h" // V_SQ_CF_INDEX_NONE/0/1
40
41 namespace r600_sb {
42
43 rp_kcache_tracker::rp_kcache_tracker(shader &sh) : rp(), uc(),
44 // FIXME: for now we'll use "two const pairs" limit for r600, same as
45 // for other chips, otherwise additional check in alu_group_tracker is
46 // required to make sure that all 4 consts in the group fit into 2
47 // kcache sets
48 sel_count(2) {}
49
50 bool rp_kcache_tracker::try_reserve(sel_chan r) {
51 unsigned sel = kc_sel(r);
52
53 for (unsigned i = 0; i < sel_count; ++i) {
54 if (rp[i] == 0) {
55 rp[i] = sel;
56 ++uc[i];
57 return true;
58 }
59 if (rp[i] == sel) {
60 ++uc[i];
61 return true;
62 }
63 }
64 return false;
65 }
66
67 bool rp_kcache_tracker::try_reserve(node* n) {
68 bool need_unreserve = false;
69 vvec::iterator I(n->src.begin()), E(n->src.end());
70
71 for (; I != E; ++I) {
72 value *v = *I;
73 if (v->is_kcache()) {
74 if (!try_reserve(v->select))
75 break;
76 else
77 need_unreserve = true;
78 }
79 }
80 if (I == E)
81 return true;
82
83 if (need_unreserve && I != n->src.begin()) {
84 do {
85 --I;
86 value *v =*I;
87 if (v->is_kcache())
88 unreserve(v->select);
89 } while (I != n->src.begin());
90 }
91 return false;
92 }
93
94 inline
95 void rp_kcache_tracker::unreserve(node* n) {
96 vvec::iterator I(n->src.begin()), E(n->src.end());
97 for (; I != E; ++I) {
98 value *v = *I;
99 if (v->is_kcache())
100 unreserve(v->select);
101 }
102 }
103
104 void rp_kcache_tracker::unreserve(sel_chan r) {
105 unsigned sel = kc_sel(r);
106
107 for (unsigned i = 0; i < sel_count; ++i)
108 if (rp[i] == sel) {
109 if (--uc[i] == 0)
110 rp[i] = 0;
111 return;
112 }
113 assert(0);
114 return;
115 }
116
117 bool literal_tracker::try_reserve(alu_node* n) {
118 bool need_unreserve = false;
119
120 vvec::iterator I(n->src.begin()), E(n->src.end());
121
122 for (; I != E; ++I) {
123 value *v = *I;
124 if (v->is_literal()) {
125 if (!try_reserve(v->literal_value))
126 break;
127 else
128 need_unreserve = true;
129 }
130 }
131 if (I == E)
132 return true;
133
134 if (need_unreserve && I != n->src.begin()) {
135 do {
136 --I;
137 value *v =*I;
138 if (v->is_literal())
139 unreserve(v->literal_value);
140 } while (I != n->src.begin());
141 }
142 return false;
143 }
144
145 void literal_tracker::unreserve(alu_node* n) {
146 unsigned nsrc = n->bc.op_ptr->src_count, i;
147
148 for (i = 0; i < nsrc; ++i) {
149 value *v = n->src[i];
150 if (v->is_literal())
151 unreserve(v->literal_value);
152 }
153 }
154
155 bool literal_tracker::try_reserve(literal l) {
156
157 PSC_DUMP( sblog << "literal reserve " << l.u << " " << l.f << "\n"; );
158
159 for (unsigned i = 0; i < MAX_ALU_LITERALS; ++i) {
160 if (lt[i] == 0) {
161 lt[i] = l;
162 ++uc[i];
163 PSC_DUMP( sblog << " reserved new uc = " << uc[i] << "\n"; );
164 return true;
165 } else if (lt[i] == l) {
166 ++uc[i];
167 PSC_DUMP( sblog << " reserved uc = " << uc[i] << "\n"; );
168 return true;
169 }
170 }
171 PSC_DUMP( sblog << " failed to reserve literal\n"; );
172 return false;
173 }
174
175 void literal_tracker::unreserve(literal l) {
176
177 PSC_DUMP( sblog << "literal unreserve " << l.u << " " << l.f << "\n"; );
178
179 for (unsigned i = 0; i < MAX_ALU_LITERALS; ++i) {
180 if (lt[i] == l) {
181 if (--uc[i] == 0)
182 lt[i] = 0;
183 return;
184 }
185 }
186 assert(0);
187 return;
188 }
189
190 static inline unsigned bs_cycle_vector(unsigned bs, unsigned src) {
191 static const unsigned swz[VEC_NUM][3] = {
192 {0, 1, 2}, {0, 2, 1}, {1, 2, 0}, {1, 0, 2}, {2, 0, 1}, {2, 1, 0}
193 };
194 assert(bs < VEC_NUM && src < 3);
195 return swz[bs][src];
196 }
197
198 static inline unsigned bs_cycle_scalar(unsigned bs, unsigned src) {
199 static const unsigned swz[SCL_NUM][3] = {
200 {2, 1, 0}, {1, 2, 2}, {2, 1, 2}, {2, 2, 1}
201 };
202
203 if (bs >= SCL_NUM || src >= 3) {
204 // this prevents gcc warning "array subscript is above array bounds"
205 // AFAICS we should never hit this path
206 abort();
207 }
208 return swz[bs][src];
209 }
210
211 static inline unsigned bs_cycle(bool trans, unsigned bs, unsigned src) {
212 return trans ? bs_cycle_scalar(bs, src) : bs_cycle_vector(bs, src);
213 }
214
215 inline
216 bool rp_gpr_tracker::try_reserve(unsigned cycle, unsigned sel, unsigned chan) {
217 ++sel;
218 if (rp[cycle][chan] == 0) {
219 rp[cycle][chan] = sel;
220 ++uc[cycle][chan];
221 return true;
222 } else if (rp[cycle][chan] == sel) {
223 ++uc[cycle][chan];
224 return true;
225 }
226 return false;
227 }
228
229 inline
230 void rp_gpr_tracker::unreserve(alu_node* n) {
231 unsigned nsrc = n->bc.op_ptr->src_count, i;
232 unsigned trans = n->bc.slot == SLOT_TRANS;
233 unsigned bs = n->bc.bank_swizzle;
234 unsigned opt = !trans
235 && n->bc.src[0].sel == n->bc.src[1].sel
236 && n->bc.src[0].chan == n->bc.src[1].chan;
237
238 for (i = 0; i < nsrc; ++i) {
239 value *v = n->src[i];
240 if (v->is_readonly() || v->is_undef())
241 continue;
242 if (i == 1 && opt)
243 continue;
244 unsigned cycle = bs_cycle(trans, bs, i);
245 unreserve(cycle, n->bc.src[i].sel, n->bc.src[i].chan);
246 }
247 }
248
249 inline
250 void rp_gpr_tracker::unreserve(unsigned cycle, unsigned sel, unsigned chan) {
251 ++sel;
252 assert(rp[cycle][chan] == sel && uc[cycle][chan]);
253 if (--uc[cycle][chan] == 0)
254 rp[cycle][chan] = 0;
255 }
256
257 inline
258 bool rp_gpr_tracker::try_reserve(alu_node* n) {
259 unsigned nsrc = n->bc.op_ptr->src_count, i;
260 unsigned trans = n->bc.slot == SLOT_TRANS;
261 unsigned bs = n->bc.bank_swizzle;
262 unsigned opt = !trans && nsrc >= 2 &&
263 n->src[0] == n->src[1];
264
265 bool need_unreserve = false;
266 unsigned const_count = 0, min_gpr_cycle = 3;
267
268 for (i = 0; i < nsrc; ++i) {
269 value *v = n->src[i];
270 if (v->is_readonly() || v->is_undef()) {
271 const_count++;
272 if (trans && const_count == 3)
273 break;
274 } else {
275 if (i == 1 && opt)
276 continue;
277
278 unsigned cycle = bs_cycle(trans, bs, i);
279
280 if (trans && cycle < min_gpr_cycle)
281 min_gpr_cycle = cycle;
282
283 if (const_count && cycle < const_count && trans)
284 break;
285
286 if (!try_reserve(cycle, n->bc.src[i].sel, n->bc.src[i].chan))
287 break;
288 else
289 need_unreserve = true;
290 }
291 }
292
293 if ((i == nsrc) && (min_gpr_cycle + 1 > const_count))
294 return true;
295
296 if (need_unreserve && i--) {
297 do {
298 value *v = n->src[i];
299 if (!v->is_readonly() && !v->is_undef()) {
300 if (i == 1 && opt)
301 continue;
302 unreserve(bs_cycle(trans, bs, i), n->bc.src[i].sel,
303 n->bc.src[i].chan);
304 }
305 } while (i--);
306 }
307 return false;
308 }
309
310 alu_group_tracker::alu_group_tracker(shader &sh)
311 : sh(sh), kc(sh),
312 gpr(), lt(), slots(),
313 max_slots(sh.get_ctx().is_cayman() ? 4 : 5),
314 has_mova(), uses_ar(), has_predset(), has_kill(),
315 updates_exec_mask(), chan_count(), interp_param(), next_id() {
316
317 available_slots = sh.get_ctx().has_trans ? 0x1F : 0x0F;
318 }
319
320 inline
321 sel_chan alu_group_tracker::get_value_id(value* v) {
322 unsigned &id = vmap[v];
323 if (!id)
324 id = ++next_id;
325 return sel_chan(id, v->get_final_chan());
326 }
327
328 inline
329 void alu_group_tracker::assign_slot(unsigned slot, alu_node* n) {
330 update_flags(n);
331 slots[slot] = n;
332 available_slots &= ~(1 << slot);
333
334 unsigned param = n->interp_param();
335
336 if (param) {
337 assert(!interp_param || interp_param == param);
338 interp_param = param;
339 }
340 }
341
342
343 void alu_group_tracker::discard_all_slots(container_node &removed_nodes) {
344 PSC_DUMP( sblog << "agt::discard_all_slots\n"; );
345 discard_slots(~available_slots & ((1 << max_slots) - 1), removed_nodes);
346 }
347
348 void alu_group_tracker::discard_slots(unsigned slot_mask,
349 container_node &removed_nodes) {
350
351 PSC_DUMP(
352 sblog << "discard_slots : packed_ops : "
353 << (unsigned)packed_ops.size() << "\n";
354 );
355
356 for (node_vec::iterator N, I = packed_ops.begin();
357 I != packed_ops.end(); I = N) {
358 N = I; ++N;
359
360 alu_packed_node *n = static_cast<alu_packed_node*>(*I);
361 unsigned pslots = n->get_slot_mask();
362
363 PSC_DUMP(
364 sblog << "discard_slots : packed slot_mask : " << pslots << "\n";
365 );
366
367 if (pslots & slot_mask) {
368
369 PSC_DUMP(
370 sblog << "discard_slots : discarding packed...\n";
371 );
372
373 removed_nodes.push_back(n);
374 slot_mask &= ~pslots;
375 N = packed_ops.erase(I);
376 available_slots |= pslots;
377 for (unsigned k = 0; k < max_slots; ++k) {
378 if (pslots & (1 << k))
379 slots[k] = NULL;
380 }
381 }
382 }
383
384 for (unsigned slot = 0; slot < max_slots; ++slot) {
385 unsigned slot_bit = 1 << slot;
386
387 if (slot_mask & slot_bit) {
388 assert(!(available_slots & slot_bit));
389 assert(slots[slot]);
390
391 assert(!(slots[slot]->bc.slot_flags & AF_4SLOT));
392
393 PSC_DUMP(
394 sblog << "discarding slot " << slot << " : ";
395 dump::dump_op(slots[slot]);
396 sblog << "\n";
397 );
398
399 removed_nodes.push_back(slots[slot]);
400 slots[slot] = NULL;
401 available_slots |= slot_bit;
402 }
403 }
404
405 alu_node *t = slots[4];
406 if (t && (t->bc.slot_flags & AF_V)) {
407 unsigned chan = t->bc.dst_chan;
408 if (!slots[chan]) {
409 PSC_DUMP(
410 sblog << "moving ";
411 dump::dump_op(t);
412 sblog << " from trans slot to free slot " << chan << "\n";
413 );
414
415 slots[chan] = t;
416 slots[4] = NULL;
417 t->bc.slot = chan;
418 }
419 }
420
421 reinit();
422 }
423
424 alu_group_node* alu_group_tracker::emit() {
425
426 alu_group_node *g = sh.create_alu_group();
427
428 lt.init_group_literals(g);
429
430 for (unsigned i = 0; i < max_slots; ++i) {
431 alu_node *n = slots[i];
432 if (n) {
433 g->push_back(n);
434 }
435 }
436 return g;
437 }
438
439 bool alu_group_tracker::try_reserve(alu_node* n) {
440 unsigned nsrc = n->bc.op_ptr->src_count;
441 unsigned slot = n->bc.slot;
442 bool trans = slot == 4;
443
444 if (slots[slot])
445 return false;
446
447 unsigned flags = n->bc.op_ptr->flags;
448
449 unsigned param = n->interp_param();
450
451 if (param && interp_param && interp_param != param)
452 return false;
453
454 if ((flags & AF_KILL) && has_predset)
455 return false;
456 if ((flags & AF_ANY_PRED) && (has_kill || has_predset))
457 return false;
458 if ((flags & AF_MOVA) && (has_mova || uses_ar))
459 return false;
460
461 if (n->uses_ar() && has_mova)
462 return false;
463
464 for (unsigned i = 0; i < nsrc; ++i) {
465
466 unsigned last_id = next_id;
467
468 value *v = n->src[i];
469 if (!v->is_any_gpr() && !v->is_rel())
470 continue;
471 sel_chan vid = get_value_id(n->src[i]);
472
473 if (vid > last_id && chan_count[vid.chan()] == 3) {
474 return false;
475 }
476
477 n->bc.src[i].sel = vid.sel();
478 n->bc.src[i].chan = vid.chan();
479 }
480
481 if (!lt.try_reserve(n))
482 return false;
483
484 if (!kc.try_reserve(n)) {
485 lt.unreserve(n);
486 return false;
487 }
488
489 unsigned fbs = n->forced_bank_swizzle();
490
491 n->bc.bank_swizzle = 0;
492
493 if (!trans && fbs)
494 n->bc.bank_swizzle = VEC_210;
495
496 if (gpr.try_reserve(n)) {
497 assign_slot(slot, n);
498 return true;
499 }
500
501 if (!fbs) {
502 unsigned swz_num = trans ? SCL_NUM : VEC_NUM;
503 for (unsigned bs = 0; bs < swz_num; ++bs) {
504 n->bc.bank_swizzle = bs;
505 if (gpr.try_reserve(n)) {
506 assign_slot(slot, n);
507 return true;
508 }
509 }
510 }
511
512 gpr.reset();
513
514 slots[slot] = n;
515 unsigned forced_swz_slots = 0;
516 int first_slot = ~0, first_nf = ~0, last_slot = ~0;
517 unsigned save_bs[5];
518
519 for (unsigned i = 0; i < max_slots; ++i) {
520 alu_node *a = slots[i];
521 if (a) {
522 if (first_slot == ~0)
523 first_slot = i;
524 last_slot = i;
525 save_bs[i] = a->bc.bank_swizzle;
526 if (a->forced_bank_swizzle()) {
527 assert(i != SLOT_TRANS);
528 forced_swz_slots |= (1 << i);
529 a->bc.bank_swizzle = VEC_210;
530 if (!gpr.try_reserve(a))
531 assert(!"internal reservation error");
532 } else {
533 if (first_nf == ~0)
534 first_nf = i;
535
536 a->bc.bank_swizzle = 0;
537 }
538 }
539 }
540
541 if (first_nf == ~0) {
542 assign_slot(slot, n);
543 return true;
544 }
545
546 assert(first_slot != ~0 && last_slot != ~0);
547
548 // silence "array subscript is above array bounds" with gcc 4.8
549 if (last_slot >= 5)
550 abort();
551
552 int i = first_nf;
553 alu_node *a = slots[i];
554 bool backtrack = false;
555
556 while (1) {
557
558 PSC_DUMP(
559 sblog << " bs: trying s" << i << " bs:" << a->bc.bank_swizzle
560 << " bt:" << backtrack << "\n";
561 );
562
563 if (!backtrack && gpr.try_reserve(a)) {
564 PSC_DUMP(
565 sblog << " bs: reserved s" << i << " bs:" << a->bc.bank_swizzle
566 << "\n";
567 );
568
569 while ((++i <= last_slot) && !slots[i]);
570 if (i <= last_slot)
571 a = slots[i];
572 else
573 break;
574 } else {
575 bool itrans = i == SLOT_TRANS;
576 unsigned max_swz = itrans ? SCL_221 : VEC_210;
577
578 if (a->bc.bank_swizzle < max_swz) {
579 ++a->bc.bank_swizzle;
580
581 PSC_DUMP(
582 sblog << " bs: inc s" << i << " bs:" << a->bc.bank_swizzle
583 << "\n";
584 );
585
586 } else {
587
588 a->bc.bank_swizzle = 0;
589 while ((--i >= first_nf) && !slots[i]);
590 if (i < first_nf)
591 break;
592 a = slots[i];
593 PSC_DUMP(
594 sblog << " bs: unreserve s" << i << " bs:" << a->bc.bank_swizzle
595 << "\n";
596 );
597 gpr.unreserve(a);
598 backtrack = true;
599
600 continue;
601 }
602 }
603 backtrack = false;
604 }
605
606 if (i == last_slot + 1) {
607 assign_slot(slot, n);
608 return true;
609 }
610
611 // reservation failed, restore previous state
612 slots[slot] = NULL;
613 gpr.reset();
614 for (unsigned i = 0; i < max_slots; ++i) {
615 alu_node *a = slots[i];
616 if (a) {
617 a->bc.bank_swizzle = save_bs[i];
618 bool b = gpr.try_reserve(a);
619 assert(b);
620 }
621 }
622
623 kc.unreserve(n);
624 lt.unreserve(n);
625 return false;
626 }
627
628 bool alu_group_tracker::try_reserve(alu_packed_node* p) {
629 bool need_unreserve = false;
630 node_iterator I(p->begin()), E(p->end());
631
632 for (; I != E; ++I) {
633 alu_node *n = static_cast<alu_node*>(*I);
634 if (!try_reserve(n))
635 break;
636 else
637 need_unreserve = true;
638 }
639
640 if (I == E) {
641 packed_ops.push_back(p);
642 return true;
643 }
644
645 if (need_unreserve) {
646 while (--I != E) {
647 alu_node *n = static_cast<alu_node*>(*I);
648 slots[n->bc.slot] = NULL;
649 }
650 reinit();
651 }
652 return false;
653 }
654
655 void alu_group_tracker::reinit() {
656 alu_node * s[5];
657 memcpy(s, slots, sizeof(slots));
658
659 reset(true);
660
661 for (int i = max_slots - 1; i >= 0; --i) {
662 if (s[i] && !try_reserve(s[i])) {
663 sblog << "alu_group_tracker: reinit error on slot " << i << "\n";
664 for (unsigned i = 0; i < max_slots; ++i) {
665 sblog << " slot " << i << " : ";
666 if (s[i])
667 dump::dump_op(s[i]);
668
669 sblog << "\n";
670 }
671 assert(!"alu_group_tracker: reinit error");
672 }
673 }
674 }
675
676 void alu_group_tracker::reset(bool keep_packed) {
677 kc.reset();
678 gpr.reset();
679 lt.reset();
680 memset(slots, 0, sizeof(slots));
681 vmap.clear();
682 next_id = 0;
683 has_mova = false;
684 uses_ar = false;
685 has_predset = false;
686 has_kill = false;
687 updates_exec_mask = false;
688 available_slots = sh.get_ctx().has_trans ? 0x1F : 0x0F;
689 interp_param = 0;
690
691 chan_count[0] = 0;
692 chan_count[1] = 0;
693 chan_count[2] = 0;
694 chan_count[3] = 0;
695
696 if (!keep_packed)
697 packed_ops.clear();
698 }
699
700 void alu_group_tracker::update_flags(alu_node* n) {
701 unsigned flags = n->bc.op_ptr->flags;
702 has_kill |= (flags & AF_KILL);
703 has_mova |= (flags & AF_MOVA);
704 has_predset |= (flags & AF_ANY_PRED);
705 uses_ar |= n->uses_ar();
706
707 if (flags & AF_ANY_PRED) {
708 if (n->dst[2] != NULL)
709 updates_exec_mask = true;
710 }
711 }
712
713 int post_scheduler::run() {
714 return run_on(sh.root) ? 0 : 1;
715 }
716
717 bool post_scheduler::run_on(container_node* n) {
718 int r = true;
719 for (node_riterator I = n->rbegin(), E = n->rend(); I != E; ++I) {
720 if (I->is_container()) {
721 if (I->subtype == NST_BB) {
722 bb_node* bb = static_cast<bb_node*>(*I);
723 r = schedule_bb(bb);
724 } else {
725 r = run_on(static_cast<container_node*>(*I));
726 }
727 if (!r)
728 break;
729 }
730 }
731 return r;
732 }
733
734 void post_scheduler::init_uc_val(container_node *c, value *v) {
735 node *d = v->any_def();
736 if (d && d->parent == c)
737 ++ucm[d];
738 }
739
740 void post_scheduler::init_uc_vec(container_node *c, vvec &vv, bool src) {
741 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
742 value *v = *I;
743 if (!v || v->is_readonly())
744 continue;
745
746 if (v->is_rel()) {
747 init_uc_val(c, v->rel);
748 init_uc_vec(c, v->muse, true);
749 } if (src) {
750 init_uc_val(c, v);
751 }
752 }
753 }
754
755 unsigned post_scheduler::init_ucm(container_node *c, node *n) {
756 init_uc_vec(c, n->src, true);
757 init_uc_vec(c, n->dst, false);
758
759 uc_map::iterator F = ucm.find(n);
760 return F == ucm.end() ? 0 : F->second;
761 }
762
763 bool post_scheduler::schedule_bb(bb_node* bb) {
764 PSC_DUMP(
765 sblog << "scheduling BB " << bb->id << "\n";
766 if (!pending.empty())
767 dump::dump_op_list(&pending);
768 );
769
770 assert(pending.empty());
771 assert(bb_pending.empty());
772 assert(ready.empty());
773
774 bb_pending.append_from(bb);
775 cur_bb = bb;
776
777 node *n;
778
779 while ((n = bb_pending.back())) {
780
781 PSC_DUMP(
782 sblog << "post_sched_bb ";
783 dump::dump_op(n);
784 sblog << "\n";
785 );
786
787 // May require emitting ALU ops to load index registers
788 if (n->is_fetch_clause()) {
789 n->remove();
790 process_fetch(static_cast<container_node *>(n));
791 continue;
792 }
793
794 if (n->is_alu_clause()) {
795 n->remove();
796 bool r = process_alu(static_cast<container_node*>(n));
797 if (r)
798 continue;
799 return false;
800 }
801
802 n->remove();
803 bb->push_front(n);
804 }
805
806 this->cur_bb = NULL;
807 return true;
808 }
809
810 void post_scheduler::init_regmap() {
811
812 regmap.clear();
813
814 PSC_DUMP(
815 sblog << "init_regmap: live: ";
816 dump::dump_set(sh, live);
817 sblog << "\n";
818 );
819
820 for (val_set::iterator I = live.begin(sh), E = live.end(sh); I != E; ++I) {
821 value *v = *I;
822 assert(v);
823 if (!v->is_sgpr() || !v->is_prealloc())
824 continue;
825
826 sel_chan r = v->gpr;
827
828 PSC_DUMP(
829 sblog << "init_regmap: " << r << " <= ";
830 dump::dump_val(v);
831 sblog << "\n";
832 );
833
834 assert(r);
835 regmap[r] = v;
836 }
837 }
838
839 static alu_node *create_set_idx(shader &sh, unsigned ar_idx) {
840 alu_node *a = sh.create_alu();
841
842 assert(ar_idx == V_SQ_CF_INDEX_0 || ar_idx == V_SQ_CF_INDEX_1);
843 if (ar_idx == V_SQ_CF_INDEX_0)
844 a->bc.set_op(ALU_OP0_SET_CF_IDX0);
845 else
846 a->bc.set_op(ALU_OP0_SET_CF_IDX1);
847 a->bc.slot = SLOT_X;
848 a->dst.resize(1); // Dummy needed for recolor
849
850 PSC_DUMP(
851 sblog << "created IDX load: ";
852 dump::dump_op(a);
853 sblog << "\n";
854 );
855
856 return a;
857 }
858
859 void post_scheduler::load_index_register(value *v, unsigned ar_idx)
860 {
861 alu.reset();
862
863 if (!sh.get_ctx().is_cayman()) {
864 // Evergreen has to first load address register, then use CF_SET_IDX0/1
865 alu_group_tracker &rt = alu.grp();
866 alu_node *set_idx = create_set_idx(sh, ar_idx);
867 if (!rt.try_reserve(set_idx)) {
868 sblog << "can't emit SET_CF_IDX";
869 dump::dump_op(set_idx);
870 sblog << "\n";
871 }
872 process_group();
873
874 if (!alu.check_clause_limits()) {
875 // Can't happen since clause only contains MOVA/CF_SET_IDX0/1
876 }
877 alu.emit_group();
878 }
879
880 alu_group_tracker &rt = alu.grp();
881 alu_node *a = alu.create_ar_load(v, ar_idx == V_SQ_CF_INDEX_1 ? SEL_Z : SEL_Y);
882
883 if (!rt.try_reserve(a)) {
884 sblog << "can't emit AR load : ";
885 dump::dump_op(a);
886 sblog << "\n";
887 }
888
889 process_group();
890
891 if (!alu.check_clause_limits()) {
892 // Can't happen since clause only contains MOVA/CF_SET_IDX0/1
893 }
894
895 alu.emit_group();
896 alu.emit_clause(cur_bb);
897 }
898
899 void post_scheduler::process_fetch(container_node *c) {
900 if (c->empty())
901 return;
902
903 for (node_iterator N, I = c->begin(), E = c->end(); I != E; I = N) {
904 N = I;
905 ++N;
906
907 node *n = *I;
908
909 fetch_node *f = static_cast<fetch_node*>(n);
910
911 PSC_DUMP(
912 sblog << "process_tex ";
913 dump::dump_op(n);
914 sblog << " ";
915 );
916
917 // TODO: If same values used can avoid reloading index register
918 if (f->bc.sampler_index_mode != V_SQ_CF_INDEX_NONE ||
919 f->bc.resource_index_mode != V_SQ_CF_INDEX_NONE) {
920 unsigned index_mode = f->bc.sampler_index_mode != V_SQ_CF_INDEX_NONE ?
921 f->bc.sampler_index_mode : f->bc.resource_index_mode;
922
923 // Currently require prior opt passes to use one TEX per indexed op
924 assert(f->parent->count() == 1);
925
926 value *v = f->src.back(); // Last src is index offset
927 assert(v);
928
929 cur_bb->push_front(c);
930
931 load_index_register(v, index_mode);
932 f->src.pop_back(); // Don't need index value any more
933
934 return;
935 }
936 }
937
938 cur_bb->push_front(c);
939 }
940
941 bool post_scheduler::process_alu(container_node *c) {
942
943 if (c->empty())
944 return true;
945
946 ucm.clear();
947 alu.reset();
948
949 live = c->live_after;
950
951 init_globals(c->live_after, true);
952 init_globals(c->live_before, true);
953
954 init_regmap();
955
956 update_local_interferences();
957
958 for (node_riterator N, I = c->rbegin(), E = c->rend(); I != E; I = N) {
959 N = I;
960 ++N;
961
962 node *n = *I;
963 unsigned uc = init_ucm(c, n);
964
965 PSC_DUMP(
966 sblog << "process_alu uc=" << uc << " ";
967 dump::dump_op(n);
968 sblog << " ";
969 );
970
971 if (uc) {
972 n->remove();
973
974 pending.push_back(n);
975 PSC_DUMP( sblog << "pending\n"; );
976 } else {
977 release_op(n);
978 }
979 }
980
981 return schedule_alu(c);
982 }
983
984 void post_scheduler::update_local_interferences() {
985
986 PSC_DUMP(
987 sblog << "update_local_interferences : ";
988 dump::dump_set(sh, live);
989 sblog << "\n";
990 );
991
992
993 for (val_set::iterator I = live.begin(sh), E = live.end(sh); I != E; ++I) {
994 value *v = *I;
995 if (v->is_prealloc())
996 continue;
997
998 v->interferences.add_set(live);
999 }
1000 }
1001
1002 void post_scheduler::update_live_src_vec(vvec &vv, val_set *born, bool src) {
1003 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1004 value *v = *I;
1005
1006 if (!v)
1007 continue;
1008
1009 if (src && v->is_any_gpr()) {
1010 if (live.add_val(v)) {
1011 if (!v->is_prealloc()) {
1012 if (!cleared_interf.contains(v)) {
1013 PSC_DUMP(
1014 sblog << "clearing interferences for " << *v << "\n";
1015 );
1016 v->interferences.clear();
1017 cleared_interf.add_val(v);
1018 }
1019 }
1020 if (born)
1021 born->add_val(v);
1022 }
1023 } else if (v->is_rel()) {
1024 if (!v->rel->is_any_gpr())
1025 live.add_val(v->rel);
1026 update_live_src_vec(v->muse, born, true);
1027 }
1028 }
1029 }
1030
1031 void post_scheduler::update_live_dst_vec(vvec &vv) {
1032 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1033 value *v = *I;
1034 if (!v)
1035 continue;
1036
1037 if (v->is_rel()) {
1038 update_live_dst_vec(v->mdef);
1039 } else if (v->is_any_gpr()) {
1040 if (!live.remove_val(v)) {
1041 PSC_DUMP(
1042 sblog << "failed to remove ";
1043 dump::dump_val(v);
1044 sblog << " from live : ";
1045 dump::dump_set(sh, live);
1046 sblog << "\n";
1047 );
1048 }
1049 }
1050 }
1051 }
1052
1053 void post_scheduler::update_live(node *n, val_set *born) {
1054 update_live_dst_vec(n->dst);
1055 update_live_src_vec(n->src, born, true);
1056 update_live_src_vec(n->dst, born, false);
1057 }
1058
1059 void post_scheduler::process_group() {
1060 alu_group_tracker &rt = alu.grp();
1061
1062 val_set vals_born;
1063
1064 recolor_locals();
1065
1066 PSC_DUMP(
1067 sblog << "process_group: live_before : ";
1068 dump::dump_set(sh, live);
1069 sblog << "\n";
1070 );
1071
1072 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1073 alu_node *n = rt.slot(s);
1074 if (!n)
1075 continue;
1076
1077 update_live(n, &vals_born);
1078 }
1079
1080 PSC_DUMP(
1081 sblog << "process_group: live_after : ";
1082 dump::dump_set(sh, live);
1083 sblog << "\n";
1084 );
1085
1086 update_local_interferences();
1087
1088 for (unsigned i = 0; i < 5; ++i) {
1089 node *n = rt.slot(i);
1090 if (n && !n->is_mova()) {
1091 release_src_values(n);
1092 }
1093 }
1094 }
1095
1096 void post_scheduler::init_globals(val_set &s, bool prealloc) {
1097
1098 PSC_DUMP(
1099 sblog << "init_globals: ";
1100 dump::dump_set(sh, s);
1101 sblog << "\n";
1102 );
1103
1104 for (val_set::iterator I = s.begin(sh), E = s.end(sh); I != E; ++I) {
1105 value *v = *I;
1106 if (v->is_sgpr() && !v->is_global()) {
1107 v->set_global();
1108
1109 if (prealloc && v->is_fixed()) {
1110 v->set_prealloc();
1111 }
1112 }
1113 }
1114 }
1115
1116 void post_scheduler::emit_index_registers() {
1117 for (unsigned i = 0; i < 2; i++) {
1118 if (alu.current_idx[i]) {
1119 regmap = prev_regmap;
1120 alu.discard_current_group();
1121
1122 load_index_register(alu.current_idx[i], KC_INDEX_0 + i);
1123 alu.current_idx[i] = NULL;
1124 }
1125 }
1126 }
1127
1128 void post_scheduler::emit_clause() {
1129
1130 if (alu.current_ar) {
1131 emit_load_ar();
1132 process_group();
1133 alu.emit_group();
1134 }
1135
1136 if (!alu.is_empty()) {
1137 alu.emit_clause(cur_bb);
1138 }
1139
1140 emit_index_registers();
1141 }
1142
1143 bool post_scheduler::schedule_alu(container_node *c) {
1144
1145 assert(!ready.empty() || !ready_copies.empty());
1146
1147 bool improving = true;
1148 int last_pending = pending.count();
1149 while (improving) {
1150 prev_regmap = regmap;
1151 if (!prepare_alu_group()) {
1152
1153 int new_pending = pending.count();
1154 improving = (new_pending < last_pending) || (last_pending == 0);
1155 last_pending = new_pending;
1156
1157 if (alu.current_idx[0] || alu.current_idx[1]) {
1158 regmap = prev_regmap;
1159 emit_clause();
1160 init_globals(live, false);
1161
1162 continue;
1163 }
1164
1165 if (alu.current_ar) {
1166 emit_load_ar();
1167 continue;
1168 } else
1169 break;
1170 }
1171
1172 if (!alu.check_clause_limits()) {
1173 regmap = prev_regmap;
1174 emit_clause();
1175 init_globals(live, false);
1176
1177 continue;
1178 }
1179
1180 process_group();
1181 alu.emit_group();
1182 };
1183
1184 if (!alu.is_empty()) {
1185 emit_clause();
1186 }
1187
1188 if (!ready.empty()) {
1189 sblog << "##post_scheduler: unscheduled ready instructions :";
1190 dump::dump_op_list(&ready);
1191 assert(!"unscheduled ready instructions");
1192 }
1193
1194 if (!pending.empty()) {
1195 sblog << "##post_scheduler: unscheduled pending instructions :";
1196 dump::dump_op_list(&pending);
1197 assert(!"unscheduled pending instructions");
1198 }
1199 return improving;
1200 }
1201
1202 void post_scheduler::add_interferences(value *v, sb_bitset &rb, val_set &vs) {
1203 unsigned chan = v->gpr.chan();
1204
1205 for (val_set::iterator I = vs.begin(sh), E = vs.end(sh);
1206 I != E; ++I) {
1207 value *vi = *I;
1208 sel_chan gpr = vi->get_final_gpr();
1209
1210 if (vi->is_any_gpr() && gpr && vi != v &&
1211 (!v->chunk || v->chunk != vi->chunk) &&
1212 vi->is_fixed() && gpr.chan() == chan) {
1213
1214 unsigned r = gpr.sel();
1215
1216 PSC_DUMP(
1217 sblog << "\tadd_interferences: " << *vi << "\n";
1218 );
1219
1220 if (rb.size() <= r)
1221 rb.resize(r + 32);
1222 rb.set(r);
1223 }
1224 }
1225 }
1226
1227 void post_scheduler::set_color_local_val(value *v, sel_chan color) {
1228 v->gpr = color;
1229
1230 PSC_DUMP(
1231 sblog << " recolored: ";
1232 dump::dump_val(v);
1233 sblog << "\n";
1234 );
1235 }
1236
1237 void post_scheduler::set_color_local(value *v, sel_chan color) {
1238 if (v->chunk) {
1239 vvec &vv = v->chunk->values;
1240 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1241 value *v2 =*I;
1242 set_color_local_val(v2, color);
1243 }
1244 v->chunk->fix();
1245 } else {
1246 set_color_local_val(v, color);
1247 v->fix();
1248 }
1249 }
1250
1251 bool post_scheduler::recolor_local(value *v) {
1252
1253 sb_bitset rb;
1254
1255 assert(v->is_sgpr());
1256 assert(!v->is_prealloc());
1257 assert(v->gpr);
1258
1259 unsigned chan = v->gpr.chan();
1260
1261 PSC_DUMP(
1262 sblog << "recolor_local: ";
1263 dump::dump_val(v);
1264 sblog << " interferences: ";
1265 dump::dump_set(sh, v->interferences);
1266 sblog << "\n";
1267 if (v->chunk) {
1268 sblog << " in chunk: ";
1269 coalescer::dump_chunk(v->chunk);
1270 sblog << "\n";
1271 }
1272 );
1273
1274 if (v->chunk) {
1275 for (vvec::iterator I = v->chunk->values.begin(),
1276 E = v->chunk->values.end(); I != E; ++I) {
1277 value *v2 = *I;
1278
1279 PSC_DUMP( sblog << " add_interferences for " << *v2 << " :\n"; );
1280
1281 add_interferences(v, rb, v2->interferences);
1282 }
1283 } else {
1284 add_interferences(v, rb, v->interferences);
1285 }
1286
1287 PSC_DUMP(
1288 unsigned sz = rb.size();
1289 sblog << "registers bits: " << sz;
1290 for (unsigned r = 0; r < sz; ++r) {
1291 if ((r & 7) == 0)
1292 sblog << "\n " << r << " ";
1293 sblog << (rb.get(r) ? 1 : 0);
1294 }
1295 );
1296
1297 bool no_temp_gprs = v->is_global();
1298 unsigned rs, re, pass = no_temp_gprs ? 1 : 0;
1299
1300 while (pass < 2) {
1301
1302 if (pass == 0) {
1303 rs = sh.first_temp_gpr();
1304 re = MAX_GPR;
1305 } else {
1306 rs = 0;
1307 re = sh.num_nontemp_gpr();
1308 }
1309
1310 for (unsigned reg = rs; reg < re; ++reg) {
1311 if (reg >= rb.size() || !rb.get(reg)) {
1312 // color found
1313 set_color_local(v, sel_chan(reg, chan));
1314 return true;
1315 }
1316 }
1317 ++pass;
1318 }
1319
1320 assert(!"recolor_local failed");
1321 return true;
1322 }
1323
1324 void post_scheduler::emit_load_ar() {
1325
1326 regmap = prev_regmap;
1327 alu.discard_current_group();
1328
1329 alu_group_tracker &rt = alu.grp();
1330 alu_node *a = alu.create_ar_load(alu.current_ar, SEL_X);
1331
1332 if (!rt.try_reserve(a)) {
1333 sblog << "can't emit AR load : ";
1334 dump::dump_op(a);
1335 sblog << "\n";
1336 }
1337
1338 alu.current_ar = 0;
1339 }
1340
1341 bool post_scheduler::unmap_dst_val(value *d) {
1342
1343 if (d == alu.current_ar) {
1344 emit_load_ar();
1345 return false;
1346 }
1347
1348 if (d->is_prealloc()) {
1349 sel_chan gpr = d->get_final_gpr();
1350 rv_map::iterator F = regmap.find(gpr);
1351 value *c = NULL;
1352 if (F != regmap.end())
1353 c = F->second;
1354
1355 if (c && c!=d && (!c->chunk || c->chunk != d->chunk)) {
1356 PSC_DUMP(
1357 sblog << "dst value conflict : ";
1358 dump::dump_val(d);
1359 sblog << " regmap contains ";
1360 dump::dump_val(c);
1361 sblog << "\n";
1362 );
1363 assert(!"scheduler error");
1364 return false;
1365 } else if (c) {
1366 regmap.erase(F);
1367 }
1368 }
1369 return true;
1370 }
1371
1372 bool post_scheduler::unmap_dst(alu_node *n) {
1373 value *d = n->dst.empty() ? NULL : n->dst[0];
1374
1375 if (!d)
1376 return true;
1377
1378 if (!d->is_rel()) {
1379 if (d && d->is_any_reg()) {
1380
1381 if (d->is_AR()) {
1382 if (alu.current_ar != d) {
1383 sblog << "loading wrong ar value\n";
1384 assert(0);
1385 } else {
1386 alu.current_ar = NULL;
1387 }
1388
1389 } else if (d->is_any_gpr()) {
1390 if (!unmap_dst_val(d))
1391 return false;
1392 }
1393 }
1394 } else {
1395 for (vvec::iterator I = d->mdef.begin(), E = d->mdef.end();
1396 I != E; ++I) {
1397 d = *I;
1398 if (!d)
1399 continue;
1400
1401 assert(d->is_any_gpr());
1402
1403 if (!unmap_dst_val(d))
1404 return false;
1405 }
1406 }
1407 return true;
1408 }
1409
1410 bool post_scheduler::map_src_val(value *v) {
1411
1412 if (!v->is_prealloc())
1413 return true;
1414
1415 sel_chan gpr = v->get_final_gpr();
1416 rv_map::iterator F = regmap.find(gpr);
1417 value *c = NULL;
1418 if (F != regmap.end()) {
1419 c = F->second;
1420 if (!v->v_equal(c)) {
1421 PSC_DUMP(
1422 sblog << "can't map src value ";
1423 dump::dump_val(v);
1424 sblog << ", regmap contains ";
1425 dump::dump_val(c);
1426 sblog << "\n";
1427 );
1428 return false;
1429 }
1430 } else {
1431 regmap.insert(std::make_pair(gpr, v));
1432 }
1433 return true;
1434 }
1435
1436 bool post_scheduler::map_src_vec(vvec &vv, bool src) {
1437 if (src) {
1438 // Handle possible UBO indexing
1439 bool ubo_indexing[2] = { false, false };
1440 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1441 value *v = *I;
1442 if (!v)
1443 continue;
1444
1445 if (v->is_kcache()) {
1446 unsigned index_mode = v->select.kcache_index_mode();
1447 if (index_mode == KC_INDEX_0 || index_mode == KC_INDEX_1) {
1448 ubo_indexing[index_mode - KC_INDEX_0] = true;
1449 }
1450 }
1451 }
1452
1453 // idx values stored at end of src vec, see bc_parser::prepare_alu_group
1454 for (unsigned i = 2; i != 0; i--) {
1455 if (ubo_indexing[i-1]) {
1456 // TODO: skip adding value to kcache reservation somehow, causes
1457 // unnecessary group breaks and cache line locks
1458 value *v = vv.back();
1459 if (alu.current_idx[i-1] && alu.current_idx[i-1] != v) {
1460 PSC_DUMP(
1461 sblog << "IDX" << i-1 << " already set to " <<
1462 *alu.current_idx[i-1] << ", trying to set " << *v << "\n";
1463 );
1464 return false;
1465 }
1466
1467 alu.current_idx[i-1] = v;
1468 PSC_DUMP(sblog << "IDX" << i-1 << " set to " << *v << "\n";);
1469 }
1470 }
1471 }
1472
1473 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1474 value *v = *I;
1475 if (!v)
1476 continue;
1477
1478 if ((!v->is_any_gpr() || !v->is_fixed()) && !v->is_rel())
1479 continue;
1480
1481 if (v->is_rel()) {
1482 value *rel = v->rel;
1483 assert(rel);
1484
1485 if (!rel->is_const()) {
1486 if (!map_src_vec(v->muse, true))
1487 return false;
1488
1489 if (rel != alu.current_ar) {
1490 if (alu.current_ar) {
1491 PSC_DUMP(
1492 sblog << " current_AR is " << *alu.current_ar
1493 << " trying to use " << *rel << "\n";
1494 );
1495 return false;
1496 }
1497
1498 alu.current_ar = rel;
1499
1500 PSC_DUMP(
1501 sblog << " new current_AR assigned: " << *alu.current_ar
1502 << "\n";
1503 );
1504 }
1505 }
1506
1507 } else if (src) {
1508 if (!map_src_val(v)) {
1509 return false;
1510 }
1511 }
1512 }
1513 return true;
1514 }
1515
1516 bool post_scheduler::map_src(alu_node *n) {
1517 if (!map_src_vec(n->dst, false))
1518 return false;
1519
1520 if (!map_src_vec(n->src, true))
1521 return false;
1522
1523 return true;
1524 }
1525
1526 void post_scheduler::dump_regmap() {
1527
1528 sblog << "# REGMAP :\n";
1529
1530 for(rv_map::iterator I = regmap.begin(), E = regmap.end(); I != E; ++I) {
1531 sblog << " # " << I->first << " => " << *(I->second) << "\n";
1532 }
1533
1534 if (alu.current_ar)
1535 sblog << " current_AR: " << *alu.current_ar << "\n";
1536 if (alu.current_pr)
1537 sblog << " current_PR: " << *alu.current_pr << "\n";
1538 if (alu.current_idx[0])
1539 sblog << " current IDX0: " << *alu.current_idx[0] << "\n";
1540 if (alu.current_idx[1])
1541 sblog << " current IDX1: " << *alu.current_idx[1] << "\n";
1542 }
1543
1544 void post_scheduler::recolor_locals() {
1545 alu_group_tracker &rt = alu.grp();
1546
1547 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1548 alu_node *n = rt.slot(s);
1549 if (n) {
1550 value *d = n->dst[0];
1551 if (d && d->is_sgpr() && !d->is_prealloc()) {
1552 recolor_local(d);
1553 }
1554 }
1555 }
1556 }
1557
1558 // returns true if there are interferences
1559 bool post_scheduler::check_interferences() {
1560
1561 alu_group_tracker &rt = alu.grp();
1562
1563 unsigned interf_slots;
1564
1565 bool discarded = false;
1566
1567 PSC_DUMP(
1568 sblog << "check_interferences: before: \n";
1569 dump_regmap();
1570 );
1571
1572 do {
1573
1574 interf_slots = 0;
1575
1576 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1577 alu_node *n = rt.slot(s);
1578 if (n) {
1579 if (!unmap_dst(n)) {
1580 return true;
1581 }
1582 }
1583 }
1584
1585 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1586 alu_node *n = rt.slot(s);
1587 if (n) {
1588 if (!map_src(n)) {
1589 interf_slots |= (1 << s);
1590 }
1591 }
1592 }
1593
1594 PSC_DUMP(
1595 for (unsigned i = 0; i < 5; ++i) {
1596 if (interf_slots & (1 << i)) {
1597 sblog << "!!!!!! interf slot: " << i << " : ";
1598 dump::dump_op(rt.slot(i));
1599 sblog << "\n";
1600 }
1601 }
1602 );
1603
1604 if (!interf_slots)
1605 break;
1606
1607 PSC_DUMP( sblog << "ci: discarding slots " << interf_slots << "\n"; );
1608
1609 rt.discard_slots(interf_slots, alu.conflict_nodes);
1610 regmap = prev_regmap;
1611 discarded = true;
1612
1613 } while(1);
1614
1615 PSC_DUMP(
1616 sblog << "check_interferences: after: \n";
1617 dump_regmap();
1618 );
1619
1620 return discarded;
1621 }
1622
1623 // add instruction(s) (alu_node or contents of alu_packed_node) to current group
1624 // returns the number of added instructions on success
1625 unsigned post_scheduler::try_add_instruction(node *n) {
1626
1627 alu_group_tracker &rt = alu.grp();
1628
1629 unsigned avail_slots = rt.avail_slots();
1630
1631 // Cannot schedule in same clause as instructions using this index value
1632 if (!n->dst.empty() && n->dst[0] &&
1633 (n->dst[0] == alu.current_idx[0] || n->dst[0] == alu.current_idx[1])) {
1634 PSC_DUMP(sblog << " CF_IDX source: " << *n->dst[0] << "\n";);
1635 return 0;
1636 }
1637
1638 if (n->is_alu_packed()) {
1639 alu_packed_node *p = static_cast<alu_packed_node*>(n);
1640 unsigned slots = p->get_slot_mask();
1641 unsigned cnt = __builtin_popcount(slots);
1642
1643 if ((slots & avail_slots) != slots) {
1644 PSC_DUMP( sblog << " no slots \n"; );
1645 return 0;
1646 }
1647
1648 p->update_packed_items(ctx);
1649
1650 if (!rt.try_reserve(p)) {
1651 PSC_DUMP( sblog << " reservation failed \n"; );
1652 return 0;
1653 }
1654
1655 p->remove();
1656 return cnt;
1657
1658 } else {
1659 alu_node *a = static_cast<alu_node*>(n);
1660 value *d = a->dst.empty() ? NULL : a->dst[0];
1661
1662 if (d && d->is_special_reg()) {
1663 assert((a->bc.op_ptr->flags & AF_MOVA) || d->is_geometry_emit());
1664 d = NULL;
1665 }
1666
1667 unsigned allowed_slots = ctx.alu_slots_mask(a->bc.op_ptr);
1668 unsigned slot;
1669
1670 allowed_slots &= avail_slots;
1671
1672 if (!allowed_slots)
1673 return 0;
1674
1675 if (d) {
1676 slot = d->get_final_chan();
1677 a->bc.dst_chan = slot;
1678 allowed_slots &= (1 << slot) | 0x10;
1679 } else {
1680 if (a->bc.op_ptr->flags & AF_MOVA) {
1681 if (a->bc.slot_flags & AF_V)
1682 allowed_slots &= (1 << SLOT_X);
1683 else
1684 allowed_slots &= (1 << SLOT_TRANS);
1685 }
1686 }
1687
1688 // FIXME workaround for some problems with MULADD in trans slot on r700,
1689 // (is it really needed on r600?)
1690 if ((a->bc.op == ALU_OP3_MULADD || a->bc.op == ALU_OP3_MULADD_IEEE) &&
1691 !ctx.is_egcm()) {
1692 allowed_slots &= 0x0F;
1693 }
1694
1695 if (!allowed_slots) {
1696 PSC_DUMP( sblog << " no suitable slots\n"; );
1697 return 0;
1698 }
1699
1700 slot = __builtin_ctz(allowed_slots);
1701 a->bc.slot = slot;
1702
1703 PSC_DUMP( sblog << "slot: " << slot << "\n"; );
1704
1705 if (!rt.try_reserve(a)) {
1706 PSC_DUMP( sblog << " reservation failed\n"; );
1707 return 0;
1708 }
1709
1710 a->remove();
1711 return 1;
1712 }
1713 }
1714
1715 bool post_scheduler::check_copy(node *n) {
1716 if (!n->is_copy_mov())
1717 return false;
1718
1719 value *s = n->src[0];
1720 value *d = n->dst[0];
1721
1722 if (!s->is_sgpr() || !d->is_sgpr())
1723 return false;
1724
1725 if (!s->is_prealloc()) {
1726 recolor_local(s);
1727
1728 if (!s->chunk || s->chunk != d->chunk)
1729 return false;
1730 }
1731
1732 if (s->gpr == d->gpr) {
1733
1734 PSC_DUMP(
1735 sblog << "check_copy: ";
1736 dump::dump_op(n);
1737 sblog << "\n";
1738 );
1739
1740 rv_map::iterator F = regmap.find(d->gpr);
1741 bool gpr_free = (F == regmap.end());
1742
1743 if (d->is_prealloc()) {
1744 if (gpr_free) {
1745 PSC_DUMP( sblog << " copy not ready...\n";);
1746 return true;
1747 }
1748
1749 value *rv = F->second;
1750 if (rv != d && (!rv->chunk || rv->chunk != d->chunk)) {
1751 PSC_DUMP( sblog << " copy not ready(2)...\n";);
1752 return true;
1753 }
1754
1755 unmap_dst(static_cast<alu_node*>(n));
1756 }
1757
1758 if (s->is_prealloc() && !map_src_val(s))
1759 return true;
1760
1761 update_live(n, NULL);
1762
1763 release_src_values(n);
1764 n->remove();
1765 PSC_DUMP( sblog << " copy coalesced...\n";);
1766 return true;
1767 }
1768 return false;
1769 }
1770
1771 void post_scheduler::dump_group(alu_group_tracker &rt) {
1772 for (unsigned i = 0; i < 5; ++i) {
1773 node *n = rt.slot(i);
1774 if (n) {
1775 sblog << "slot " << i << " : ";
1776 dump::dump_op(n);
1777 sblog << "\n";
1778 }
1779 }
1780 }
1781
1782 void post_scheduler::process_ready_copies() {
1783
1784 node *last;
1785
1786 do {
1787 last = ready_copies.back();
1788
1789 for (node_iterator N, I = ready_copies.begin(), E = ready_copies.end();
1790 I != E; I = N) {
1791 N = I; ++N;
1792
1793 node *n = *I;
1794
1795 if (!check_copy(n)) {
1796 n->remove();
1797 ready.push_back(n);
1798 }
1799 }
1800 } while (last != ready_copies.back());
1801
1802 update_local_interferences();
1803 }
1804
1805
1806 bool post_scheduler::prepare_alu_group() {
1807
1808 alu_group_tracker &rt = alu.grp();
1809
1810 unsigned i1 = 0;
1811
1812 PSC_DUMP(
1813 sblog << "prepare_alu_group: starting...\n";
1814 dump_group(rt);
1815 );
1816
1817 ready.append_from(&alu.conflict_nodes);
1818
1819 // FIXME rework this loop
1820
1821 do {
1822
1823 process_ready_copies();
1824
1825 ++i1;
1826
1827 for (node_iterator N, I = ready.begin(), E = ready.end(); I != E;
1828 I = N) {
1829 N = I; ++N;
1830 node *n = *I;
1831
1832 PSC_DUMP(
1833 sblog << "p_a_g: ";
1834 dump::dump_op(n);
1835 sblog << "\n";
1836 );
1837
1838
1839 unsigned cnt = try_add_instruction(n);
1840
1841 if (!cnt)
1842 continue;
1843
1844 PSC_DUMP(
1845 sblog << "current group:\n";
1846 dump_group(rt);
1847 );
1848
1849 if (rt.inst_count() == ctx.num_slots) {
1850 PSC_DUMP( sblog << " all slots used\n"; );
1851 break;
1852 }
1853 }
1854
1855 if (!check_interferences())
1856 break;
1857
1858 // don't try to add more instructions to the group with mova if this
1859 // can lead to breaking clause slot count limit - we don't want mova to
1860 // end up in the end of the new clause instead of beginning of the
1861 // current clause.
1862 if (rt.has_ar_load() && alu.total_slots() > 121)
1863 break;
1864
1865 if (rt.inst_count() && i1 > 50)
1866 break;
1867
1868 regmap = prev_regmap;
1869
1870 } while (1);
1871
1872 PSC_DUMP(
1873 sblog << " prepare_alu_group done, " << rt.inst_count()
1874 << " slot(s) \n";
1875
1876 sblog << "$$$$$$$$PAG i1=" << i1
1877 << " ready " << ready.count()
1878 << " pending " << pending.count()
1879 << " conflicting " << alu.conflict_nodes.count()
1880 <<"\n";
1881
1882 );
1883
1884 return rt.inst_count();
1885 }
1886
1887 void post_scheduler::release_src_values(node* n) {
1888 release_src_vec(n->src, true);
1889 release_src_vec(n->dst, false);
1890 }
1891
1892 void post_scheduler::release_op(node *n) {
1893 PSC_DUMP(
1894 sblog << "release_op ";
1895 dump::dump_op(n);
1896 sblog << "\n";
1897 );
1898
1899 n->remove();
1900
1901 if (n->is_copy_mov()) {
1902 ready_copies.push_back(n);
1903 } else if (n->is_mova() || n->is_pred_set()) {
1904 ready.push_front(n);
1905 } else {
1906 ready.push_back(n);
1907 }
1908 }
1909
1910 void post_scheduler::release_src_val(value *v) {
1911 node *d = v->any_def();
1912 if (d) {
1913 if (!--ucm[d])
1914 release_op(d);
1915 }
1916 }
1917
1918 void post_scheduler::release_src_vec(vvec& vv, bool src) {
1919
1920 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1921 value *v = *I;
1922 if (!v || v->is_readonly())
1923 continue;
1924
1925 if (v->is_rel()) {
1926 release_src_val(v->rel);
1927 release_src_vec(v->muse, true);
1928
1929 } else if (src) {
1930 release_src_val(v);
1931 }
1932 }
1933 }
1934
1935 void literal_tracker::reset() {
1936 memset(lt, 0, sizeof(lt));
1937 memset(uc, 0, sizeof(uc));
1938 }
1939
1940 void rp_gpr_tracker::reset() {
1941 memset(rp, 0, sizeof(rp));
1942 memset(uc, 0, sizeof(uc));
1943 }
1944
1945 void rp_kcache_tracker::reset() {
1946 memset(rp, 0, sizeof(rp));
1947 memset(uc, 0, sizeof(uc));
1948 }
1949
1950 void alu_kcache_tracker::reset() {
1951 memset(kc, 0, sizeof(kc));
1952 lines.clear();
1953 }
1954
1955 void alu_clause_tracker::reset() {
1956 group = 0;
1957 slot_count = 0;
1958 grp0.reset();
1959 grp1.reset();
1960 }
1961
1962 alu_clause_tracker::alu_clause_tracker(shader &sh)
1963 : sh(sh), kt(sh.get_ctx().hw_class), slot_count(),
1964 grp0(sh), grp1(sh),
1965 group(), clause(),
1966 push_exec_mask(),
1967 current_ar(), current_pr(), current_idx() {}
1968
1969 void alu_clause_tracker::emit_group() {
1970
1971 assert(grp().inst_count());
1972
1973 alu_group_node *g = grp().emit();
1974
1975 if (grp().has_update_exec_mask()) {
1976 assert(!push_exec_mask);
1977 push_exec_mask = true;
1978 }
1979
1980 assert(g);
1981
1982 if (!clause) {
1983 clause = sh.create_clause(NST_ALU_CLAUSE);
1984 }
1985
1986 clause->push_front(g);
1987
1988 slot_count += grp().slot_count();
1989
1990 new_group();
1991
1992 PSC_DUMP( sblog << " #### group emitted\n"; );
1993 }
1994
1995 void alu_clause_tracker::emit_clause(container_node *c) {
1996 assert(clause);
1997
1998 kt.init_clause(clause->bc);
1999
2000 assert(!current_ar);
2001 assert(!current_pr);
2002
2003 if (push_exec_mask)
2004 clause->bc.set_op(CF_OP_ALU_PUSH_BEFORE);
2005
2006 c->push_front(clause);
2007
2008 clause = NULL;
2009 push_exec_mask = false;
2010 slot_count = 0;
2011 kt.reset();
2012
2013 PSC_DUMP( sblog << "######### ALU clause emitted\n"; );
2014 }
2015
2016 bool alu_clause_tracker::check_clause_limits() {
2017
2018 alu_group_tracker &gt = grp();
2019
2020 unsigned slots = gt.slot_count();
2021
2022 // reserving slots to load AR and PR values
2023 unsigned reserve_slots = (current_ar ? 1 : 0) + (current_pr ? 1 : 0);
2024 // ...and index registers
2025 reserve_slots += (current_idx[0] != NULL) + (current_idx[1] != NULL);
2026
2027 if (slot_count + slots > MAX_ALU_SLOTS - reserve_slots)
2028 return false;
2029
2030 if (!kt.try_reserve(gt))
2031 return false;
2032
2033 return true;
2034 }
2035
2036 void alu_clause_tracker::new_group() {
2037 group = !group;
2038 grp().reset();
2039 }
2040
2041 bool alu_clause_tracker::is_empty() {
2042 return clause == NULL;
2043 }
2044
2045 void literal_tracker::init_group_literals(alu_group_node* g) {
2046
2047 g->literals.clear();
2048 for (unsigned i = 0; i < 4; ++i) {
2049 if (!lt[i])
2050 break;
2051
2052 g->literals.push_back(lt[i]);
2053
2054 PSC_DUMP(
2055 sblog << "literal emitted: " << lt[i].f;
2056 sblog.print_zw_hex(lt[i].u, 8);
2057 sblog << " " << lt[i].i << "\n";
2058 );
2059 }
2060 }
2061
2062 bool alu_kcache_tracker::try_reserve(alu_group_tracker& gt) {
2063 rp_kcache_tracker &kt = gt.kcache();
2064
2065 if (!kt.num_sels())
2066 return true;
2067
2068 sb_set<unsigned> group_lines;
2069
2070 unsigned nl = kt.get_lines(group_lines);
2071 assert(nl);
2072
2073 sb_set<unsigned> clause_lines(lines);
2074 lines.add_set(group_lines);
2075
2076 if (clause_lines.size() == lines.size())
2077 return true;
2078
2079 if (update_kc())
2080 return true;
2081
2082 lines = clause_lines;
2083
2084 return false;
2085 }
2086
2087 unsigned rp_kcache_tracker::get_lines(kc_lines& lines) {
2088 unsigned cnt = 0;
2089
2090 for (unsigned i = 0; i < sel_count; ++i) {
2091 unsigned line = rp[i] & 0x1fffffffu;
2092 unsigned index_mode = rp[i] >> 29;
2093
2094 if (!line)
2095 return cnt;
2096
2097 --line;
2098 line = (sel_count == 2) ? line >> 5 : line >> 6;
2099 line |= index_mode << 29;
2100
2101 if (lines.insert(line).second)
2102 ++cnt;
2103 }
2104 return cnt;
2105 }
2106
2107 bool alu_kcache_tracker::update_kc() {
2108 unsigned c = 0;
2109
2110 bc_kcache old_kc[4];
2111 memcpy(old_kc, kc, sizeof(kc));
2112
2113 for (kc_lines::iterator I = lines.begin(), E = lines.end(); I != E; ++I) {
2114 unsigned index_mode = *I >> 29;
2115 unsigned line = *I & 0x1fffffffu;
2116 unsigned bank = line >> 8;
2117
2118 assert(index_mode <= KC_INDEX_INVALID);
2119 line &= 0xFF;
2120
2121 if (c && (bank == kc[c-1].bank) && (kc[c-1].addr + 1 == line) &&
2122 kc[c-1].index_mode == index_mode)
2123 {
2124 kc[c-1].mode = KC_LOCK_2;
2125 } else {
2126 if (c == max_kcs) {
2127 memcpy(kc, old_kc, sizeof(kc));
2128 return false;
2129 }
2130
2131 kc[c].mode = KC_LOCK_1;
2132
2133 kc[c].bank = bank;
2134 kc[c].addr = line;
2135 kc[c].index_mode = index_mode;
2136 ++c;
2137 }
2138 }
2139 return true;
2140 }
2141
2142 alu_node* alu_clause_tracker::create_ar_load(value *v, chan_select ar_channel) {
2143 alu_node *a = sh.create_alu();
2144
2145 if (sh.get_ctx().uses_mova_gpr) {
2146 a->bc.set_op(ALU_OP1_MOVA_GPR_INT);
2147 a->bc.slot = SLOT_TRANS;
2148 } else {
2149 a->bc.set_op(ALU_OP1_MOVA_INT);
2150 a->bc.slot = SLOT_X;
2151 }
2152 a->bc.dst_chan = ar_channel;
2153 if (ar_channel != SEL_X && sh.get_ctx().is_cayman()) {
2154 a->bc.dst_gpr = ar_channel == SEL_Y ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1;
2155 }
2156
2157 a->dst.resize(1);
2158 a->src.push_back(v);
2159
2160 PSC_DUMP(
2161 sblog << "created AR load: ";
2162 dump::dump_op(a);
2163 sblog << "\n";
2164 );
2165
2166 return a;
2167 }
2168
2169 void alu_clause_tracker::discard_current_group() {
2170 PSC_DUMP( sblog << "act::discard_current_group\n"; );
2171 grp().discard_all_slots(conflict_nodes);
2172 }
2173
2174 void rp_gpr_tracker::dump() {
2175 sblog << "=== gpr_tracker dump:\n";
2176 for (int c = 0; c < 3; ++c) {
2177 sblog << "cycle " << c << " ";
2178 for (int h = 0; h < 4; ++h) {
2179 sblog << rp[c][h] << ":" << uc[c][h] << " ";
2180 }
2181 sblog << "\n";
2182 }
2183 }
2184
2185 } // namespace r600_sb