r600/sfn: rework getting a vector and uniforms from the value pool
[mesa.git] / src / gallium / drivers / r600 / sfn / sfn_defines.h
1 /* -*- mesa-c++ -*-
2 *
3 * Copyright (c) 2018-2019 Collabora LTD
4 *
5 * Author: Gert Wollny <gert.wollny@collabora.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #ifndef sfn_defines_h
28 #define sfn_defines_h
29
30 #include "../r600_isa.h"
31 #include "amd_family.h"
32 namespace r600 {
33
34
35 enum EGWSOpCode {
36 cf_sema_v = 0,
37 cf_sema_p = 1,
38 cf_gws_barrier = 2,
39 cf_gws_init = 3,
40 };
41
42 /* CF ALU instructions [29:26], highest bit always set. */
43 enum ECFAluOpCode {
44 cf_alu_undefined = 0,
45 cf_alu = CF_OP_ALU,
46 cf_alu_push_before = CF_OP_ALU_PUSH_BEFORE,
47 cf_alu_pop_after = CF_OP_ALU_POP_AFTER,
48 cf_alu_pop2_after = CF_OP_ALU_POP2_AFTER,
49 cf_alu_extended = CF_OP_ALU_EXT,
50 cf_alu_continue = CF_OP_ALU_CONTINUE,
51 cf_alu_break = CF_OP_ALU_BREAK,
52 cf_alu_else_after = CF_OP_ALU_ELSE_AFTER,
53 };
54
55 enum ECFAluOpCodeEG {
56 eg_cf_alu_undefined = 0,
57 eg_cf_alu = 8,
58 eg_cf_alu_push_before = 9,
59 eg_cf_alu_pop_after = 10,
60 eg_cf_alu_pop2_after = 11,
61 eg_cf_alu_extended = 12,
62 eg_cf_alu_continue = 13,
63 eg_cf_alu_break = 14,
64 eg_cf_alu_else_after = 15,
65 };
66
67
68 enum ECFOpCode {
69 cf_nop = CF_OP_NOP,
70 cf_tc = CF_OP_TEX,
71 cf_vc = CF_OP_VTX,
72 cf_gds = CF_OP_GDS,
73 cf_loop_start = CF_OP_LOOP_START,
74 cf_loop_end = CF_OP_LOOP_END,
75 cf_loop_start_dx10 = CF_OP_LOOP_START_DX10,
76 cf_loop_start_no_al = CF_OP_LOOP_START_NO_AL,
77 cf_loop_continue = CF_OP_LOOP_CONTINUE,
78 cf_loop_break = CF_OP_LOOP_BREAK,
79 cf_jump = CF_OP_JUMP,
80 cf_push = CF_OP_PUSH,
81 cf_else = CF_OP_ELSE,
82 cf_pop = CF_OP_POP,
83 /* 15 - 17 reserved */
84 cf_call = CF_OP_CALL,
85 cf_call_fs = CF_OP_CALL_FS,
86 cf_return = CF_OP_RET,
87 cf_emit_vertex = CF_OP_EMIT_VERTEX,
88 cf_emit_cut_vertex = CF_OP_EMIT_CUT_VERTEX,
89 cf_cut_vertex = CF_OP_CUT_VERTEX,
90 cf_kill = CF_OP_KILL,
91 /* 25 reserved */
92 cf_wait_ack = CF_OP_WAIT_ACK,
93 cf_tc_ack = CF_OP_TEX_ACK,
94 cf_vc_ack = CF_OP_VTX_ACK,
95 cf_jump_table = CF_OP_JUMPTABLE,
96 cf_global_wave_sync = CF_OP_WAVE_SYNC,
97 cf_halt = CF_OP_HALT,
98 /* gap 32-63*/
99 cf_mem_stream0_buf0 = CF_OP_MEM_STREAM0_BUF0,
100 cf_mem_stream0_buf1 = CF_OP_MEM_STREAM0_BUF1,
101 cf_mem_stream0_buf2 = CF_OP_MEM_STREAM0_BUF2,
102 cf_mem_stream0_buf3 = CF_OP_MEM_STREAM0_BUF3,
103
104 cf_mem_stream1_buf0 = CF_OP_MEM_STREAM1_BUF0,
105 cf_mem_stream1_buf1 = CF_OP_MEM_STREAM1_BUF1,
106 cf_mem_stream1_buf2 = CF_OP_MEM_STREAM1_BUF2,
107 cf_mem_stream1_buf3 = CF_OP_MEM_STREAM1_BUF3,
108
109 cf_mem_stream2_buf0 = CF_OP_MEM_STREAM2_BUF0,
110 cf_mem_stream2_buf1 = CF_OP_MEM_STREAM2_BUF1,
111 cf_mem_stream2_buf2 = CF_OP_MEM_STREAM2_BUF2,
112 cf_mem_stream2_buf3 = CF_OP_MEM_STREAM2_BUF3,
113
114 cf_mem_stream3_buf0 = CF_OP_MEM_STREAM3_BUF0,
115 cf_mem_stream3_buf1 = CF_OP_MEM_STREAM3_BUF1,
116 cf_mem_stream3_buf2 = CF_OP_MEM_STREAM3_BUF2,
117 cf_mem_stream3_buf3 = CF_OP_MEM_STREAM3_BUF3,
118
119 cf_mem_write_scratch = CF_OP_MEM_SCRATCH ,
120 /* reserved 81 */
121 cf_mem_ring = CF_OP_MEM_RING,
122 cf_export = CF_OP_EXPORT,
123 cf_export_done = CF_OP_EXPORT_DONE,
124 cf_mem_export = CF_OP_MEM_EXPORT,
125 cf_mem_rat = CF_OP_MEM_RAT,
126 cf_mem_rat_cacheless = CF_OP_MEM_RAT_NOCACHE,
127
128 cf_mem_ring1 = CF_OP_MEM_RING1,
129 cf_mem_ring2 = CF_OP_MEM_RING2,
130 cf_mem_ring3 = CF_OP_MEM_RING3,
131 cf_mem_export_combined = CF_OP_MEM_MEM_COMBINED,
132 cf_mem_rat_combined_cacheless = CF_OP_MEM_RAT_COMBINED_NOCACHE
133
134 };
135
136 enum ECFOpCodeEG {
137 eg_cf_nop = 0,
138 eg_cf_tc = 1,
139 eg_cf_vc = 2,
140 eg_cf_gds = 3,
141 eg_cf_loop_start = 4,
142 eg_cf_loop_end = 5,
143 eg_cf_loop_start_dx10 = 6,
144 eg_cf_loop_start_no_al = 7,
145 eg_cf_loop_continue = 8,
146 eg_cf_loop_break = 9,
147 eg_cf_jump = 10,
148 eg_cf_push = 11,
149 eg_cf_else = 13,
150 eg_cf_pop = 14,
151 /* 15 - 17 reserved */
152 eg_cf_call = 18,
153 eg_cf_call_fs,
154 eg_cf_return,
155 eg_cf_emit_vertex,
156 eg_cf_emit_cut_vertex,
157 eg_cf_cut_vertex,
158 eg_cf_kill,
159 /* 25 reserved */
160 eg_cf_wait_ack = 26,
161 eg_cf_tc_ack,
162 eg_cf_vc_ack,
163 eg_cf_jump_table,
164 eg_cf_global_wave_sync,
165 eg_cf_halt,
166 /* gap 32-63*/
167 eg_cf_mem_stream0_buf0 = 64,
168 eg_cf_mem_stream0_buf1,
169 eg_cf_mem_stream0_buf2,
170 eg_cf_mem_stream0_buf3,
171
172 eg_cf_mem_stream1_buf0,
173 eg_cf_mem_stream1_buf1,
174 eg_cf_mem_stream1_buf2,
175 eg_cf_mem_stream1_buf3,
176
177 eg_cf_mem_stream2_buf0,
178 eg_cf_mem_stream2_buf1,
179 eg_cf_mem_stream2_buf2,
180 eg_cf_mem_stream2_buf3,
181
182 eg_cf_mem_stream3_buf0,
183 eg_cf_mem_stream3_buf1,
184 eg_cf_mem_stream3_buf2,
185 eg_cf_mem_stream3_buf3,
186
187 eg_cf_mem_write_scratch,
188 /* reserved 81 */
189 eg_cf_mem_ring = 82,
190 eg_cf_export,
191 eg_cf_export_done,
192 eg_cf_mem_export,
193 eg_cf_mem_rat,
194 eg_cf_mem_rat_cacheless,
195
196 eg_cf_mem_ring1,
197 eg_cf_mem_ring2,
198 eg_cf_mem_ring3,
199 eg_cf_mem_export_combined,
200 eg_cf_mem_rat_combined_cacheless
201 };
202
203
204 enum EVFetchInstr {
205 vc_fetch = FETCH_OP_VFETCH,
206 vc_semantic = FETCH_OP_SEMFETCH,
207 vc_get_buf_resinfo = FETCH_OP_GET_BUFFER_RESINFO,
208 vc_read_scratch = FETCH_OP_READ_SCRATCH,
209 vc_unknown
210 };
211
212 enum EVFetchType {
213 vertex_data = 0,
214 instance_data = 1,
215 no_index_offset = 2
216 };
217
218 enum EVTXDataFormat {
219 fmt_invalid = 0,
220 fmt_8 = 1,
221 fmt_4_4 = 2,
222 fmt_3_3_2 = 3,
223 fmt_reserved_4 = 4,
224 fmt_16 = 5,
225 fmt_16_float = 6,
226 fmt_8_8 = 7,
227 fmt_5_6_5 = 8,
228 fmt_6_5_5 = 9,
229 fmt_1_5_5_5 = 10,
230 fmt_4_4_4_4 = 11,
231 fmt_5_5_5_1 = 12,
232 fmt_32 = 13,
233 fmt_32_float = 14,
234 fmt_16_16 = 15,
235 fmt_16_16_float = 16,
236 fmt_8_24 = 17,
237 fmt_8_24_float = 18,
238 fmt_24_8 = 19,
239 fmt_24_8_float = 20,
240 fmt_10_11_11 = 21,
241 fmt_10_11_11_float = 22,
242 fmt_11_11_10 = 23,
243 fmt_11_11_10_float = 24,
244 fmt_2_10_10_10 = 25,
245 fmt_8_8_8_8 = 26,
246 fmt_10_10_10_2 = 27,
247 fmt_x24_8_32_float = 28,
248 fmt_32_32 = 29,
249 fmt_32_32_float = 30,
250 fmt_16_16_16_16 = 31,
251 fmt_16_16_16_16_float = 32,
252 fmt_reserved_33 = 33,
253 fmt_32_32_32_32 = 34,
254 fmt_32_32_32_32_float = 35,
255 fmt_reserved_36 = 36,
256 fmt_1 = 37,
257 fmt_1_reversed = 38,
258 fmt_gb_gr = 39,
259 fmt_bg_rg = 40,
260 fmt_32_as_8 = 41,
261 fmt_32_as_8_8 = 42,
262 fmt_5_9_9_9_sharedexp = 43,
263 fmt_8_8_8 = 44,
264 fmt_16_16_16 = 45,
265 fmt_16_16_16_float = 46,
266 fmt_32_32_32 = 47,
267 fmt_32_32_32_float = 48,
268 fmt_bc1 = 49,
269 fmt_bc2 = 50,
270 fmt_bc3 = 51,
271 fmt_bc4 = 52,
272 fmt_bc5 = 53,
273 fmt_apc0 = 54,
274 fmt_apc1 = 55,
275 fmt_apc2 = 56,
276 fmt_apc3 = 57,
277 fmt_apc4 = 58,
278 fmt_apc5 = 59,
279 fmt_apc6 = 60,
280 fmt_apc7 = 61,
281 fmt_ctx1 = 62,
282 fmt_reserved_63 = 63
283 };
284
285 enum EVFetchNumFormat {
286 vtx_nf_norm = 0,
287 vtx_nf_int = 1,
288 vtx_nf_scaled = 2
289 };
290
291 enum EVFetchEndianSwap {
292 vtx_es_none = 0,
293 vtx_es_8in16 = 1,
294 vtx_es_8in32 = 2
295 };
296
297 enum EVFetchFlagShift {
298 vtx_fetch_whole_quad,
299 vtx_use_const_field,
300 vtx_format_comp_signed,
301 vtx_srf_mode,
302 vtx_buf_no_stride,
303 vtx_alt_const,
304 vtx_use_tc,
305 vtx_vpm,
306 vtx_unknwon
307 };
308
309 enum EBufferIndexMode {
310 bim_none,
311 bim_zero,
312 bim_one,
313 bim_invalid
314 };
315
316 }
317
318 #endif // DEFINES_H