3 This code is an attempt to implement a NIR backend for r600.
7 piglits glsl-1.10 - 3.3 and gl-1.* gl-2.* and gl-3.* pass mostly like with TGSI, there are some fixes but
8 also a few regressions.
10 ## Currently missing features w.r.t. TGSI:
13 - compute shader support
15 - work group shared values
18 ## Needed optimizations:
20 - Register allocator and scheduler (Could the sb allocator and scheduler
24 - compare + set predicate
27 - Moves from inputs are usually not required, they could be forwarded
28 - texture operations often move additional parameters in extra registers
29 but they are actually needed in the same registes they come from and
30 could just be swizzled into the right place
31 (lower in NIR like it is done in e.g. in ETNAVIV)
36 - figure out what is wrong with the textcoord semantics: disabling it results in
37 varyings beyond the supporteed VAR31, and enabling it lets some shaders with
40 - UBOs have a strange behaviour: with
41 glsl-1.50/uniform_buffer/gs-mat4x3.shader_test
43 ADD TEMP[1].xyz = CONST[1][0].xyzz CONST[1][1].xyzz
45 vec4 ssa_12 = intrinsic load_ubo(_r600) (0, 0)(0 , 4 ,0)
46 vec4 ssa_13 = intrinsic load_ubo(_r600) (0, 1)(0 , 4 ,0)
47 vec3 ssa_14 = fadd ssa_12.xyw, ssa_13.xyw
48 so why is the "w" component emitted?
52 - multi-function shaders, how to deal with them? fp64 seems to have lots
53 of them, one option is to inline them
55 - can type information from variables be harvested?
57 lowering passes in NIR:
58 - TESS IO address evaluation should be lowered
62 The idea is to create two conversions: a NIR to a new R600 IR that
63 can be used to run some finalizing optimizations (replacing the
64 need for r600/sb) and the binary code generation.
66 The implementation uses C++ to separate the code for the different
67 shader types and the byte code generation backends. The initial attempt
68 will use the already available r600_asm code