src/gallium/drivers/r600/sfn/sfn_emitinstruction.cpp

   1 /* -*- mesa-c++  -*-
   2  *
   3  * Copyright (c) 2019 Collabora LTD
   4  *
   5  * Author: Gert Wollny <gert.wollny@collabora.com>
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "sfn_emitinstruction.h"
  28
  29 #include "sfn_shader_base.h"
  30
  31 namespace r600 {
  32
  33 EmitInstruction::EmitInstruction(ShaderFromNirProcessor& processor):
  34    m_proc(processor)
  35 {
  36
  37 }
  38
  39 EmitInstruction::~EmitInstruction()
  40 {
  41 }
  42
  43 bool EmitInstruction::emit(nir_instr* instr)
  44 {
  45    return do_emit(instr);
  46 }
  47
  48 PValue EmitInstruction::from_nir(const nir_src& v, unsigned component, unsigned swizzled)
  49 {
  50    return m_proc.from_nir(v, component, swizzled);
  51 }
  52
  53 PValue EmitInstruction::from_nir(const nir_alu_src& v, unsigned component)
  54 {
  55    return m_proc.from_nir(v, component);
  56 }
  57
  58 PValue EmitInstruction::from_nir(const nir_tex_src& v, unsigned component)
  59 {
  60    return m_proc.from_nir(v, component);
  61 }
  62
  63 PValue EmitInstruction::from_nir(const nir_alu_dest& v, unsigned component)
  64 {
  65    return m_proc.from_nir(v, component);
  66 }
  67
  68 PValue EmitInstruction::from_nir(const nir_dest& v, unsigned component)
  69 {
  70    return m_proc.from_nir(v, component);
  71 }
  72
  73 PValue EmitInstruction::from_nir(const nir_src& v, unsigned component)
  74 {
  75    return m_proc.from_nir(v, component);
  76 }
  77
  78 void EmitInstruction::emit_instruction(Instruction *ir)
  79 {
  80    return m_proc.emit_instruction(ir);
  81 }
  82
  83 bool EmitInstruction::emit_instruction(EAluOp opcode, PValue dest,
  84                                        std::vector<PValue> src0,
  85                                        const std::set<AluModifiers>& m_flags)
  86 {
  87    return m_proc.emit_instruction(opcode, dest,src0, m_flags);
  88 }
  89
  90 const nir_variable *
  91 EmitInstruction::get_deref_location(const nir_src& v) const
  92 {
  93    return m_proc.get_deref_location(v);
  94 }
  95
  96 PValue EmitInstruction::from_nir_with_fetch_constant(const nir_src& src, unsigned component, int channel)
  97 {
  98    return m_proc.from_nir_with_fetch_constant(src, component, channel);
  99 }
 100
 101 GPRVector EmitInstruction::vec_from_nir_with_fetch_constant(const nir_src& src, unsigned mask,
 102                                                             const GPRVector::Swizzle& swizzle, bool match)
 103 {
 104    return m_proc.vec_from_nir_with_fetch_constant(src, mask, swizzle, match);
 105 }
 106
 107 void EmitInstruction::add_uniform(unsigned index, const PValue &value)
 108 {
 109    m_proc.add_uniform(index, value);
 110 }
 111
 112 void EmitInstruction::load_uniform(const nir_alu_src& src)
 113 {
 114    m_proc.load_uniform(src);
 115 }
 116
 117 int EmitInstruction::lookup_register_index(const nir_src& src) const
 118 {
 119    return m_proc.lookup_register_index(src);
 120 }
 121
 122 int EmitInstruction::allocate_temp_register()
 123 {
 124    return m_proc.allocate_temp_register();
 125 }
 126
 127 int EmitInstruction::lookup_register_index(const nir_dest& dst)
 128 {
 129    return m_proc.lookup_register_index(dst);
 130 }
 131
 132 const nir_load_const_instr*
 133 EmitInstruction::get_literal_register(const nir_src& src) const
 134 {
 135    if (src.is_ssa)
 136       return m_proc.get_literal_constant(src.ssa->index);
 137    else
 138       return nullptr;
 139 }
 140
 141 PValue EmitInstruction::get_temp_register(int channel)
 142 {
 143    return m_proc.get_temp_register(channel);
 144 }
 145
 146 GPRVector EmitInstruction::get_temp_vec4()
 147 {
 148    return m_proc.get_temp_vec4();
 149 }
 150
 151 PValue EmitInstruction::create_register_from_nir_src(const nir_src& src, unsigned swizzle)
 152 {
 153    return m_proc.create_register_from_nir_src(src, swizzle);
 154 }
 155
 156 enum chip_class EmitInstruction::get_chip_class(void) const
 157 {
 158    return m_proc.get_chip_class();
 159 }
 160
 161 PValue EmitInstruction::literal(uint32_t value)
 162 {
 163    return m_proc.literal(value);
 164 }
 165
 166 GPRVector EmitInstruction::vec_from_nir(const nir_dest& dst, int num_components)
 167 {
 168    return m_proc.vec_from_nir(dst, num_components);
 169 }
 170
 171 bool EmitInstruction::inject_register(unsigned sel, unsigned swizzle,
 172                                       const PValue& reg, bool map)
 173 {
 174    return m_proc.inject_register(sel, swizzle, reg, map);
 175 }
 176
 177 int EmitInstruction::remap_atomic_base(int base)
 178 {
 179         return m_proc.remap_atomic_base(base);
 180 }
 181
 182
 183 const std::set<AluModifiers> EmitInstruction::empty = {};
 184 const std::set<AluModifiers> EmitInstruction::write = {alu_write};
 185 const std::set<AluModifiers> EmitInstruction::last_write = {alu_write, alu_last_instr};
 186 const std::set<AluModifiers> EmitInstruction::last = {alu_last_instr};
 187
 188 }
 189