9e1958f431f6b85b90ddfbeb0bbd6b4505d7bc55
[mesa.git] / src / gallium / drivers / r600 / sfn / sfn_emitinstruction.h
1 /* -*- mesa-c++ -*-
2 *
3 * Copyright (c) 2018-2019 Collabora LTD
4 *
5 * Author: Gert Wollny <gert.wollny@collabora.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #ifndef EMITINSTRUCTION_H
28 #define EMITINSTRUCTION_H
29
30 #include "compiler/nir/nir.h"
31 #include "sfn_defines.h"
32 #include "sfn_value.h"
33 #include "sfn_instruction_alu.h"
34
35 namespace r600 {
36
37 class ShaderFromNirProcessor;
38
39 class EmitInstruction
40 {
41 public:
42 EmitInstruction(ShaderFromNirProcessor& processor);
43 virtual ~EmitInstruction();
44 bool emit(nir_instr* instr);
45
46 static const std::set<AluModifiers> empty;
47 static const std::set<AluModifiers> write;
48 static const std::set<AluModifiers> last_write;
49 static const std::set<AluModifiers> last;
50
51 protected:
52 virtual bool do_emit(nir_instr* instr) = 0;
53
54 // forwards from ValuePool
55 PValue from_nir(const nir_src& v, unsigned component, unsigned swizzled);
56 PValue from_nir(const nir_src& v, unsigned component);
57 PValue from_nir(const nir_alu_src& v, unsigned component);
58 PValue from_nir(const nir_tex_src& v, unsigned component);
59 PValue from_nir(const nir_alu_dest& v, unsigned component);
60 PValue from_nir(const nir_dest& v, unsigned component);
61
62 const nir_load_const_instr* get_literal_register(const nir_src& src) const;
63
64 int lookup_register_index(const nir_src& src) const;
65 int lookup_register_index(const nir_dest& dst);
66 PValue create_register_from_nir_src(const nir_src& src, unsigned comp);
67
68 int allocate_temp_register();
69
70 PValue get_temp_register(int channel = -1);
71 GPRVector get_temp_vec4();
72
73 // forwards from ShaderFromNirProcessor
74 void emit_instruction(Instruction *ir);
75 bool emit_instruction(EAluOp opcode, PValue dest,
76 std::vector<PValue> src0,
77 const std::set<AluModifiers>& m_flags);
78
79 PValue from_nir_with_fetch_constant(const nir_src& src, unsigned component);
80 GPRVector vec_from_nir_with_fetch_constant(const nir_src& src, unsigned mask,
81 const GPRVector::Swizzle& swizzle, bool match = false);
82
83 void add_uniform(unsigned index, const PValue &value);
84 void load_uniform(const nir_alu_src& src);
85 const nir_variable *get_deref_location(const nir_src& v) const;
86
87 enum chip_class get_chip_class(void) const;
88
89 PValue literal(uint32_t value);
90
91 GPRVector vec_from_nir(const nir_dest& dst, int num_components);
92
93 bool inject_register(unsigned sel, unsigned swizzle,
94 const PValue& reg, bool map);
95
96 private:
97
98 ShaderFromNirProcessor& m_proc;
99 };
100
101 }
102
103
104
105 #endif // EMITINSTRUCTION_H