src/gallium/drivers/r600/sfn/sfn_emittexinstruction.cpp

   1 /* -*- mesa-c++  -*-
   2  *
   3  * Copyright (c) 2018 Collabora LTD
   4  *
   5  * Author: Gert Wollny <gert.wollny@collabora.com>
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "sfn_emittexinstruction.h"
  28 #include "sfn_shader_base.h"
  29 #include "sfn_instruction_fetch.h"
  30
  31 namespace r600 {
  32
  33 EmitTexInstruction::EmitTexInstruction(ShaderFromNirProcessor &processor):
  34    EmitInstruction (processor)
  35 {
  36 }
  37
  38 bool EmitTexInstruction::do_emit(nir_instr* instr)
  39 {
  40    nir_tex_instr* ir = nir_instr_as_tex(instr);
  41
  42    TexInputs src;
  43    if (!get_inputs(*ir, src))
  44       return false;
  45
  46    if (ir->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
  47       switch (ir->op) {
  48       case nir_texop_tex:
  49          return emit_cube_tex(ir, src);
  50       case nir_texop_txf:
  51          return emit_cube_txf(ir, src);
  52       case nir_texop_txb:
  53          return emit_cube_txb(ir, src);
  54       case nir_texop_txl:
  55          return emit_cube_txl(ir, src);
  56       case nir_texop_txs:
  57          return emit_tex_txs(ir, src, {0,1,2,3});
  58       case nir_texop_txd:
  59          return emit_cube_txd(ir, src);
  60       case nir_texop_lod:
  61          return emit_cube_lod(ir, src);
  62       case nir_texop_tg4:
  63          return emit_cube_tg4(ir, src);
  64       case nir_texop_query_levels:
  65          return emit_tex_txs(ir, src, {3,7,7,7});
  66       default:
  67          return false;
  68       }
  69    } else if (ir->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
  70       switch (ir->op) {
  71       case nir_texop_txf:
  72          return emit_buf_txf(ir, src);
  73       case nir_texop_txs:
  74          return emit_tex_txs(ir, src, {0,1,2,3});
  75       default:
  76          return false;
  77       }
  78    } else {
  79       switch (ir->op) {
  80       case nir_texop_tex:
  81          return emit_tex_tex(ir, src);
  82       case nir_texop_txf:
  83          return emit_tex_txf(ir, src);
  84       case nir_texop_txb:
  85          return emit_tex_txb(ir, src);
  86       case nir_texop_txl:
  87          return emit_tex_txl(ir, src);
  88       case nir_texop_txd:
  89          return emit_tex_txd(ir, src);
  90       case nir_texop_txs:
  91          return emit_tex_txs(ir, src, {0,1,2,3});
  92       case nir_texop_lod:
  93          return emit_tex_lod(ir, src);
  94       case nir_texop_tg4:
  95          return emit_tex_tg4(ir, src);
  96       case nir_texop_txf_ms:
  97          return emit_tex_txf_ms(ir, src);
  98       case nir_texop_query_levels:
  99          return emit_tex_txs(ir, src, {3,7,7,7});
 100       case nir_texop_texture_samples:
 101          return emit_tex_texture_samples(ir, src, {3,7,7,7});
 102       default:
 103
 104          return false;
 105       }
 106    }
 107 }
 108
 109 bool EmitTexInstruction::emit_cube_txf(UNUSED nir_tex_instr* instr, UNUSED TexInputs &src)
 110 {
 111    return false;
 112 }
 113
 114 bool EmitTexInstruction::emit_cube_txd(nir_tex_instr* instr, TexInputs& tex_src)
 115 {
 116
 117    assert(instr->src[0].src.is_ssa);
 118
 119    r600::sfn_log << SfnLog::instr << "emit '"
 120                  << *reinterpret_cast<nir_instr*>(instr)
 121                  << "' (" << __func__ << ")\n";
 122
 123    auto tex_op = TexInstruction::sample_g;
 124
 125    std::array<PValue, 4> v;
 126    for (int i = 0; i < 4; ++i)
 127       v[i] = from_nir(instr->dest, i);
 128
 129    GPRVector cubed(v);
 130    emit_cube_prep(tex_src.coord, cubed, instr->is_array);
 131
 132    std::array<PValue,4> dst_elms;
 133    std::array<PValue,4> src_elms;
 134
 135    const uint16_t lookup[4] = {1, 0, 3, 2};
 136    for (uint16_t i = 0; i < 4; ++i) {
 137       dst_elms[i] = v[i];
 138       src_elms[i] = cubed.reg_i(lookup[i]);
 139    }
 140
 141    GPRVector empty_dst(0, {7,7,7,7});
 142
 143    if (instr->is_shadow)  {
 144       emit_instruction(new AluInstruction(op1_mov, src_elms[3], tex_src.comperator,
 145                        {alu_last_instr, alu_write}));
 146       tex_op = TexInstruction::sample_c_g;
 147    }
 148
 149
 150    PValue half(new LiteralValue(0.5f));
 151    for (int i = 0; i < 3; ++i) {
 152       emit_instruction(new AluInstruction(op2_mul_ieee, tex_src.ddx.reg_i(i), {tex_src.ddx.reg_i(i), half},
 153       {alu_last_instr, alu_write}));
 154    }
 155    for (int i = 0; i < 3; ++i) {
 156       emit_instruction(new AluInstruction(op2_mul_ieee, tex_src.ddy.reg_i(i), {tex_src.ddy.reg_i(i), half},
 157       {alu_last_instr, alu_write}));
 158    }
 159
 160    auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
 161    assert(!sampler.indirect);
 162
 163    TexInstruction *irgh = new TexInstruction(TexInstruction::set_gradient_h, empty_dst, tex_src.ddx,
 164                                              sampler.id, sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 165    irgh->set_dest_swizzle({7,7,7,7});
 166
 167    TexInstruction *irgv = new TexInstruction(TexInstruction::set_gradient_v, empty_dst, tex_src.ddy,
 168                            sampler.id, sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 169    irgv->set_dest_swizzle({7,7,7,7});
 170
 171    GPRVector dst(dst_elms);
 172    GPRVector src(src_elms);
 173    TexInstruction *ir = new TexInstruction(tex_op, dst, src, instr->sampler_index,
 174                                  sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 175
 176    set_rect_coordinate_flags(instr, ir);
 177    //set_offsets(ir, tex_src.offset);
 178
 179    emit_instruction(irgh);
 180    emit_instruction(irgv);
 181    emit_instruction(ir);
 182    return true;
 183 }
 184
 185
 186 bool EmitTexInstruction::emit_cube_txl(nir_tex_instr* instr, TexInputs& tex_src)
 187 {
 188    assert(instr->src[0].src.is_ssa);
 189
 190    if (instr->is_shadow)
 191       return false;
 192
 193    r600::sfn_log << SfnLog::instr << "emit '"
 194                  << *reinterpret_cast<nir_instr*>(instr)
 195                  << "' (" << __func__ << ")\n";
 196
 197    std::array<PValue, 4> v;
 198    for (int i = 0; i < 4; ++i)
 199       v[i] = from_nir(instr->dest, i);
 200
 201    GPRVector cubed(v);
 202    emit_cube_prep(tex_src.coord, cubed, instr->is_array);
 203
 204    std::array<PValue,4> dst_elms;
 205    std::array<PValue,4> src_elms;
 206
 207    const uint16_t lookup[4] = {1, 0, 3, 2};
 208    for (uint16_t i = 0; i < 4; ++i) {
 209       dst_elms[i] = v[i];
 210       src_elms[i] = cubed.reg_i(lookup[i]);
 211    }
 212
 213    auto *ir = new AluInstruction(op1_mov, src_elms[3], tex_src.lod,
 214                                  {alu_last_instr, alu_write});
 215    emit_instruction(ir);
 216
 217    GPRVector src(src_elms);
 218    GPRVector dst(dst_elms);
 219
 220    auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
 221    assert(!sampler.indirect);
 222
 223    auto tir = new TexInstruction(TexInstruction::sample_l, dst, src,
 224                                  sampler.id,sampler.id + R600_MAX_CONST_BUFFERS,
 225                                  tex_src.sampler_offset);
 226
 227    if (instr->is_array)
 228       tir->set_flag(TexInstruction::z_unnormalized);
 229
 230    emit_instruction(tir);
 231    return true;
 232 }
 233
 234 bool EmitTexInstruction::emit_cube_lod(nir_tex_instr* instr, TexInputs& src)
 235 {
 236    auto tex_op = TexInstruction::get_tex_lod;
 237
 238    std::array<PValue, 4> v;
 239    for (int i = 0; i < 4; ++i)
 240       v[i] = from_nir(instr->dest, i);
 241
 242    GPRVector cubed(v);
 243    emit_cube_prep(src.coord, cubed, instr->is_array);
 244
 245    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 246    assert(!sampler.indirect);
 247
 248    auto dst = make_dest(*instr);
 249    auto irt = new TexInstruction(tex_op, dst, cubed, sampler.id,
 250                                  sampler.id + R600_MAX_CONST_BUFFERS,
 251                                  src.sampler_offset);
 252
 253    emit_instruction(irt);
 254    return true;
 255
 256 }
 257
 258
 259 bool EmitTexInstruction::emit_cube_txb(nir_tex_instr* instr, TexInputs& tex_src)
 260 {
 261    assert(instr->src[0].src.is_ssa);
 262
 263    r600::sfn_log << SfnLog::instr << "emit '"
 264                  << *reinterpret_cast<nir_instr*>(instr)
 265                  << "' (" << __func__ << ")\n";
 266
 267    std::array<PValue, 4> v;
 268    for (int i = 0; i < 4; ++i)
 269       v[i] = from_nir(instr->dest, i);
 270
 271    GPRVector cubed(v);
 272    emit_cube_prep(tex_src.coord, cubed, instr->is_array);
 273
 274    std::array<PValue,4> dst_elms;
 275    std::array<PValue,4> src_elms;
 276
 277    const uint16_t lookup[4] = {1, 0, 3, 2};
 278    for (uint16_t i = 0; i < 4; ++i) {
 279       dst_elms[i] = v[i];
 280       src_elms[i] = v[lookup[i]];
 281    }
 282
 283    GPRVector src(src_elms);
 284    GPRVector dst(dst_elms);
 285
 286    auto tex_op = TexInstruction::sample_lb;
 287    if (!instr->is_shadow)  {
 288       emit_instruction(new AluInstruction(op1_mov, src_elms[3], tex_src.bias,
 289                                           {alu_last_instr, alu_write}));
 290    } else {
 291       emit_instruction(new AluInstruction(op1_mov, src_elms[3], tex_src.comperator,
 292                        {alu_last_instr, alu_write}));
 293       tex_op = TexInstruction::sample_c_lb;
 294    }
 295
 296    auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
 297    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 298
 299    auto tir = new TexInstruction(tex_op, dst, src,
 300                                  sampler.id,
 301                                  sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 302    emit_instruction(tir);
 303    return true;
 304
 305 }
 306
 307 bool EmitTexInstruction::emit_cube_tex(nir_tex_instr* instr, TexInputs& tex_src)
 308 {
 309    std::array<PValue, 4> v;
 310    for (int i = 0; i < 4; ++i)
 311       v[i] = from_nir(instr->dest, i);
 312
 313    auto tex_op = TexInstruction::sample;
 314    GPRVector cubed(v);
 315    emit_cube_prep(tex_src.coord, cubed, instr->is_array);
 316
 317    std::array<PValue,4> dst_elms;
 318    std::array<PValue,4> src_elms;
 319
 320    const uint16_t lookup[4] = {1, 0, 3, 2};
 321    for (uint16_t i = 0; i < 4; ++i) {
 322       dst_elms[i] = v[i];
 323       src_elms[i] = v[lookup[i]];
 324    }
 325
 326    if (instr->is_shadow)  {
 327       emit_instruction(new AluInstruction(op1_mov, src_elms[3], tex_src.comperator,
 328                        {alu_last_instr, alu_write}));
 329       tex_op = TexInstruction::sample_c;
 330    }
 331
 332    GPRVector dst(dst_elms);
 333    GPRVector src(src_elms);
 334
 335    auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
 336    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 337
 338    auto tir = new TexInstruction(tex_op, dst, src,
 339                                  sampler.id,
 340                                  sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 341    if (instr->is_array)
 342       tir->set_flag(TexInstruction::z_unnormalized);
 343
 344    emit_instruction(tir);
 345    return true;
 346
 347 }
 348
 349 bool EmitTexInstruction::emit_cube_prep(const GPRVector& coord, GPRVector& cubed, bool is_array)
 350 {
 351    AluInstruction *ir = nullptr;
 352    const uint16_t src0_chan[4] = {2, 2, 0, 1};
 353    const uint16_t src1_chan[4] = {1, 0, 2, 2};
 354
 355    for (int i = 0; i < 4; ++i)  {
 356       ir = new AluInstruction(op2_cube, cubed.reg_i(i), coord.reg_i(src0_chan[i]),
 357                               coord.reg_i(src1_chan[i]), {alu_write});
 358
 359       emit_instruction(ir);
 360    }
 361    ir->set_flag(alu_last_instr);
 362
 363    ir = new AluInstruction(op1_recip_ieee, cubed.reg_i(2), cubed.reg_i(2), {alu_write, alu_last_instr});
 364    ir->set_flag(alu_src0_abs);
 365    emit_instruction(ir);
 366
 367    PValue one_p_5(new LiteralValue(1.5f));
 368    for (int i = 0; i < 2; ++i)  {
 369       ir = new AluInstruction(op3_muladd, cubed.reg_i(i), cubed.reg_i(i), cubed.reg_i(2),
 370                               one_p_5, {alu_write});
 371       emit_instruction(ir);
 372    }
 373    ir->set_flag(alu_last_instr);
 374
 375    if (is_array) {
 376       auto face = cubed.reg_i(3);
 377       PValue array_index = get_temp_register();
 378
 379       ir = new AluInstruction(op1_rndne, array_index, coord.reg_i(3), {alu_write, alu_last_instr});
 380       emit_instruction(ir);
 381
 382       ir = new AluInstruction(op2_max, array_index, {array_index, Value::zero}, {alu_write, alu_last_instr});
 383       emit_instruction(ir);
 384
 385       ir = new AluInstruction(op3_muladd, face, {array_index, PValue (new LiteralValue(8.0f)), face},
 386                               {alu_write, alu_last_instr});
 387       emit_instruction(ir);
 388    }
 389
 390    return true;
 391 }
 392
 393 bool EmitTexInstruction::emit_buf_txf(nir_tex_instr* instr, TexInputs &src)
 394 {
 395    auto dst = make_dest(*instr);
 396
 397    auto ir = new FetchInstruction(vc_fetch, no_index_offset, dst, src.coord.reg_i(0), 0,
 398                                   instr->texture_index +  R600_MAX_CONST_BUFFERS,
 399                                   src.texture_offset, bim_none);
 400    ir->set_flag(vtx_use_const_field);
 401    emit_instruction(ir);
 402    return true;
 403 }
 404
 405 bool EmitTexInstruction::emit_tex_tex(nir_tex_instr* instr, TexInputs& src)
 406 {
 407
 408    r600::sfn_log << SfnLog::instr << "emit '"
 409                  << *reinterpret_cast<nir_instr*>(instr)
 410                  << "' (" << __func__ << ")\n";
 411
 412    auto tex_op = TexInstruction::sample;
 413
 414    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 415    assert(!sampler.indirect);
 416
 417    if (instr->is_shadow)  {
 418       emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3), src.comperator,
 419                        {alu_last_instr, alu_write}));
 420       tex_op = TexInstruction::sample_c;
 421    }
 422
 423    auto dst = make_dest(*instr);
 424    auto irt = new TexInstruction(tex_op, dst, src.coord, sampler.id,
 425                                  sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 426    if (instr->is_array)
 427       handle_array_index(*instr, src.coord, irt);
 428
 429    set_rect_coordinate_flags(instr, irt);
 430    set_offsets(irt, src.offset);
 431
 432    emit_instruction(irt);
 433    return true;
 434 }
 435
 436 bool EmitTexInstruction::emit_tex_txd(nir_tex_instr* instr, TexInputs& src)
 437 {
 438    r600::sfn_log << SfnLog::instr << "emit '"
 439                  << *reinterpret_cast<nir_instr*>(instr)
 440                  << "' (" << __func__ << ")\n";
 441
 442    auto tex_op = TexInstruction::sample_g;
 443    auto dst = make_dest(*instr);
 444
 445    GPRVector empty_dst(0,{7,7,7,7});
 446
 447    if (instr->is_shadow)  {
 448       emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3), src.comperator,
 449                        {alu_last_instr, alu_write}));
 450       tex_op = TexInstruction::sample_c_g;
 451    }
 452
 453    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 454    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 455
 456    TexInstruction *irgh = new TexInstruction(TexInstruction::set_gradient_h, empty_dst, src.ddx,
 457                                              sampler.id,
 458                                              sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 459    irgh->set_dest_swizzle({7,7,7,7});
 460
 461    TexInstruction *irgv = new TexInstruction(TexInstruction::set_gradient_v, empty_dst, src.ddy,
 462                            sampler.id, sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 463    irgv->set_dest_swizzle({7,7,7,7});
 464
 465    TexInstruction *ir = new TexInstruction(tex_op, dst, src.coord, sampler.id,
 466                                            sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 467    if (instr->is_array)
 468       handle_array_index(*instr, src.coord, ir);
 469
 470    set_rect_coordinate_flags(instr, ir);
 471    set_offsets(ir, src.offset);
 472
 473    emit_instruction(irgh);
 474    emit_instruction(irgv);
 475    emit_instruction(ir);
 476    return true;
 477 }
 478
 479 bool EmitTexInstruction::emit_tex_txf(nir_tex_instr* instr, TexInputs& src)
 480 {
 481    r600::sfn_log << SfnLog::instr << "emit '"
 482                  << *reinterpret_cast<nir_instr*>(instr)
 483                  << "' (" << __func__ << ")\n";
 484
 485    auto dst = make_dest(*instr);
 486
 487    if (*src.coord.reg_i(3) != *src.lod)
 488       emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3), src.lod, {alu_write, alu_last_instr}));
 489
 490    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 491    assert(!sampler.indirect);
 492
 493    /* txf doesn't need rounding for the array index, but 1D has the array index
 494     * in the z component */
 495    if (instr->is_array && instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
 496       src.coord.set_reg_i(2, src.coord.reg_i(1));
 497
 498    auto tex_ir = new TexInstruction(TexInstruction::ld, dst, src.coord,
 499                                     sampler.id,
 500                                     sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 501
 502
 503    if (src.offset) {
 504       assert(src.offset->is_ssa);
 505       AluInstruction *ir = nullptr;
 506       for (unsigned i = 0; i < src.offset->ssa->num_components; ++i) {
 507          ir = new AluInstruction(op2_add_int, src.coord.reg_i(i),
 508                   {src.coord.reg_i(i), from_nir(*src.offset, i, i)}, {alu_write});
 509          emit_instruction(ir);
 510       }
 511       if (ir)
 512          ir->set_flag(alu_last_instr);
 513    }
 514
 515    emit_instruction(tex_ir);
 516    return true;
 517 }
 518
 519 bool EmitTexInstruction::emit_tex_lod(nir_tex_instr* instr, TexInputs& src)
 520 {
 521    auto tex_op = TexInstruction::get_tex_lod;
 522
 523    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 524    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 525
 526    auto dst = make_dest(*instr);
 527    auto irt = new TexInstruction(tex_op, dst, src.coord, sampler.id,
 528                                  sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 529    irt->set_dest_swizzle({1,0,7,7});
 530    emit_instruction(irt);
 531    return true;
 532
 533 }
 534
 535 bool EmitTexInstruction::emit_tex_txl(nir_tex_instr* instr, TexInputs& src)
 536 {
 537    r600::sfn_log << SfnLog::instr << "emit '"
 538                  << *reinterpret_cast<nir_instr*>(instr)
 539                  << "' (" << __func__ << ")\n";
 540
 541    auto tex_op = TexInstruction::sample_l;
 542    emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3), src.lod,
 543                                        {alu_last_instr, alu_write}));
 544
 545    if (instr->is_shadow)  {
 546       emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(2), src.comperator,
 547                        {alu_last_instr, alu_write}));
 548       tex_op = TexInstruction::sample_c_l;
 549    }
 550
 551    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 552    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 553
 554    auto dst = make_dest(*instr);
 555    auto irt = new TexInstruction(tex_op, dst, src.coord, sampler.id,
 556                                  sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 557
 558    if (instr->is_array)
 559       handle_array_index(*instr, src.coord, irt);
 560
 561    set_rect_coordinate_flags(instr, irt);
 562    set_offsets(irt, src.offset);
 563
 564    emit_instruction(irt);
 565    return true;
 566 }
 567
 568 bool EmitTexInstruction::emit_tex_txb(nir_tex_instr* instr, TexInputs& src)
 569 {
 570    auto tex_op = TexInstruction::sample_lb;
 571
 572    std::array<uint8_t, 4> in_swizzle = {0,1,2,3};
 573
 574    emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3), src.bias,
 575                                        {alu_last_instr, alu_write}));
 576
 577    if (instr->is_shadow) {
 578       emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(2), src.comperator,
 579                                           {alu_last_instr, alu_write}));
 580       tex_op = TexInstruction::sample_c_lb;
 581    }
 582
 583    GPRVector tex_src(src.coord, in_swizzle);
 584
 585    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 586    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 587
 588    auto dst = make_dest(*instr);
 589    auto irt = new TexInstruction(tex_op, dst, tex_src, sampler.id,
 590                                  sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 591    if (instr->is_array)
 592       handle_array_index(*instr, tex_src, irt);
 593
 594    set_rect_coordinate_flags(instr, irt);
 595    set_offsets(irt, src.offset);
 596
 597    emit_instruction(irt);
 598    return true;
 599 }
 600
 601 bool EmitTexInstruction::emit_tex_txs(nir_tex_instr* instr, TexInputs& tex_src,
 602                                       const std::array<int,4>& dest_swz)
 603 {
 604    std::array<PValue,4> dst_elms;
 605    std::array<PValue,4> src_elms;
 606
 607    for (uint16_t i = 0; i < 4; ++i) {
 608       dst_elms[i] = from_nir(instr->dest, (i < instr->dest.ssa.num_components) ? i : 7);
 609    }
 610
 611    GPRVector dst(dst_elms);
 612
 613    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
 614       emit_instruction(new FetchInstruction(dst, PValue(new GPRValue(0, 7)),
 615                        instr->sampler_index + R600_MAX_CONST_BUFFERS,
 616                        bim_none));
 617    } else {
 618       for (uint16_t i = 0; i < 4; ++i)
 619          src_elms[i] =  tex_src.lod;
 620       GPRVector src(src_elms);
 621
 622       auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
 623       assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 624
 625       auto ir = new TexInstruction(TexInstruction::get_resinfo, dst, src,
 626                                    sampler.id,
 627                                    sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 628       ir->set_dest_swizzle(dest_swz);
 629       emit_instruction(ir);
 630    }
 631
 632    return true;
 633
 634 }
 635
 636 bool EmitTexInstruction::emit_tex_texture_samples(nir_tex_instr* instr, TexInputs& src,
 637                                                   const std::array<int, 4> &dest_swz)
 638 {
 639    GPRVector dest = vec_from_nir(instr->dest, nir_dest_num_components(instr->dest));
 640    GPRVector help{0,{4,4,4,4}};
 641
 642    auto dyn_offset = PValue();
 643    int res_id = R600_MAX_CONST_BUFFERS + instr->sampler_index;
 644
 645    auto ir = new TexInstruction(TexInstruction::get_nsampled, dest, help,
 646                                 0, res_id, src.sampler_offset);
 647    ir->set_dest_swizzle(dest_swz);
 648    emit_instruction(ir);
 649    return true;
 650 }
 651
 652 bool EmitTexInstruction::emit_tex_tg4(nir_tex_instr* instr, TexInputs& src)
 653 {
 654    r600::sfn_log << SfnLog::instr << "emit '"
 655                  << *reinterpret_cast<nir_instr*>(instr)
 656                  << "' (" << __func__ << ")\n";
 657
 658    TexInstruction *set_ofs = nullptr;
 659
 660    auto tex_op = TexInstruction::gather4;
 661
 662    if (instr->is_shadow)  {
 663       emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3), src.comperator,
 664                        {alu_last_instr, alu_write}));
 665       tex_op = TexInstruction::gather4_c;
 666    }
 667
 668    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 669    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 670
 671    bool literal_offset = false;
 672    if (src.offset) {
 673       literal_offset =  src.offset->is_ssa && get_literal_register(*src.offset);
 674       r600::sfn_log << SfnLog::tex << " really have offsets and they are " <<
 675                        (literal_offset ? "literal" : "varying") <<
 676                        "\n";
 677
 678       if (!literal_offset) {
 679          GPRVector::Swizzle swizzle = {4,4,4,4};
 680          for (unsigned i = 0; i < instr->coord_components; ++i)
 681             swizzle[i] = i;
 682
 683          int noffsets = instr->coord_components;
 684          if (instr->is_array)
 685             --noffsets;
 686
 687          auto ofs = vec_from_nir_with_fetch_constant(*src.offset,
 688                                                      ( 1 << noffsets) - 1,
 689                                                      swizzle);
 690          GPRVector dummy(0, {7,7,7,7});
 691          tex_op = (tex_op == TexInstruction::gather4_c) ?
 692                      TexInstruction::gather4_c_o : TexInstruction::gather4_o;
 693
 694          set_ofs = new TexInstruction(TexInstruction::set_offsets, dummy,
 695                                            ofs, sampler.id,
 696                                       sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 697          set_ofs->set_dest_swizzle({7,7,7,7});
 698       }
 699    }
 700
 701
 702    /* pre CAYMAN needs swizzle */
 703    auto dst = make_dest(*instr);
 704    auto irt = new TexInstruction(tex_op, dst, src.coord, sampler.id,
 705                                  sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 706
 707    irt->set_dest_swizzle({1,2,0,3});
 708    irt->set_gather_comp(instr->component);
 709
 710    if (instr->is_array)
 711       handle_array_index(*instr, src.coord, irt);
 712
 713    if (literal_offset) {
 714       r600::sfn_log << SfnLog::tex << "emit literal offsets\n";
 715       set_offsets(irt, src.offset);
 716    }
 717
 718    set_rect_coordinate_flags(instr, irt);
 719
 720    if (set_ofs)
 721       emit_instruction(set_ofs);
 722
 723    emit_instruction(irt);
 724    return true;
 725 }
 726
 727 bool EmitTexInstruction::emit_cube_tg4(nir_tex_instr* instr, TexInputs& tex_src)
 728 {
 729    std::array<PValue, 4> v;
 730    for (int i = 0; i < 4; ++i)
 731       v[i] = from_nir(instr->dest, i);
 732
 733    auto tex_op = TexInstruction::gather4;
 734    GPRVector cubed(v);
 735    emit_cube_prep(tex_src.coord, cubed, instr->is_array);
 736
 737    std::array<PValue,4> dst_elms;
 738    std::array<PValue,4> src_elms;
 739
 740    const uint16_t lookup[4] = {1, 0, 3, 2};
 741    for (uint16_t i = 0; i < 4; ++i) {
 742       dst_elms[i] = v[i];
 743       src_elms[i] = v[lookup[i]];
 744    }
 745
 746    if (instr->is_shadow)  {
 747       emit_instruction(new AluInstruction(op1_mov, src_elms[3], tex_src.comperator,
 748                        {alu_last_instr, alu_write}));
 749       tex_op = TexInstruction::gather4_c;
 750    }
 751
 752    GPRVector dst(dst_elms);
 753    GPRVector src(src_elms);
 754
 755    auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
 756    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 757
 758    auto tir = new TexInstruction(tex_op, dst, src, sampler.id,
 759                                  sampler.id + R600_MAX_CONST_BUFFERS, tex_src.sampler_offset);
 760
 761    tir->set_gather_comp(instr->component);
 762
 763    tir->set_dest_swizzle({1, 2, 0, 3});
 764
 765    if (instr->is_array)
 766       tir->set_flag(TexInstruction::z_unnormalized);
 767
 768    emit_instruction(tir);
 769    return true;
 770 }
 771
 772 bool EmitTexInstruction::emit_tex_txf_ms(nir_tex_instr* instr, TexInputs& src)
 773 {
 774    assert(instr->src[0].src.is_ssa);
 775
 776    r600::sfn_log << SfnLog::instr << "emit '"
 777                  << *reinterpret_cast<nir_instr*>(instr)
 778                  << "' (" << __func__ << ")\n";
 779
 780    auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
 781    assert(!sampler.indirect && "Indirect sampler selection not yet supported");
 782
 783    int sample_id = allocate_temp_register();
 784
 785    GPRVector sample_id_dest(sample_id, {0,7,7,7});
 786    PValue help(new GPRValue(sample_id, 1));
 787
 788    /* FIXME: Texture destination registers must be handled differently,
 789     * because the swizzle identfies which source componnet has to be written
 790     * at a certain position, and the target register is actually different.
 791     * At this point we just add a helper register, but for later work (scheduling
 792     * and optimization on the r600 IR level, this needs to be implemented
 793     * differently */
 794
 795
 796    emit_instruction(new AluInstruction(op1_mov, src.coord.reg_i(3),
 797                                        src.ms_index,
 798                                        {alu_write, alu_last_instr}));
 799
 800    auto tex_sample_id_ir = new TexInstruction(TexInstruction::ld, sample_id_dest, src.coord,
 801                                               sampler.id,
 802                                               sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 803    tex_sample_id_ir->set_flag(TexInstruction::x_unnormalized);
 804    tex_sample_id_ir->set_flag(TexInstruction::y_unnormalized);
 805    tex_sample_id_ir->set_flag(TexInstruction::z_unnormalized);
 806    tex_sample_id_ir->set_flag(TexInstruction::w_unnormalized);
 807    tex_sample_id_ir->set_inst_mode(1);
 808
 809    emit_instruction(tex_sample_id_ir);
 810
 811    emit_instruction(new AluInstruction(op2_mullo_int, help,
 812                                        {src.ms_index, PValue(new LiteralValue(4))},
 813                                        {alu_write, alu_last_instr}));
 814
 815    emit_instruction(new AluInstruction(op2_lshr_int, src.coord.reg_i(3),
 816                                        {sample_id_dest.reg_i(0), help},
 817                                        {alu_write, alu_last_instr}));
 818
 819    emit_instruction(new AluInstruction(op2_and_int, src.coord.reg_i(3),
 820                                        {src.coord.reg_i(3), PValue(new LiteralValue(15))},
 821                                        {alu_write, alu_last_instr}));
 822
 823    auto dst = make_dest(*instr);
 824
 825    /* txf doesn't need rounding for the array index, but 1D has the array index
 826     * in the z component */
 827    if (instr->is_array && instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
 828       src.coord.set_reg_i(2, src.coord.reg_i(1));
 829
 830    auto tex_ir = new TexInstruction(TexInstruction::ld, dst, src.coord,
 831                                     sampler.id,
 832                                     sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
 833
 834
 835    if (src.offset) {
 836       assert(src.offset->is_ssa);
 837       AluInstruction *ir = nullptr;
 838       for (unsigned i = 0; i < src.offset->ssa->num_components; ++i) {
 839          ir = new AluInstruction(op2_add_int, src.coord.reg_i(i),
 840                   {src.coord.reg_i(i), from_nir(*src.offset, i, i)}, {alu_write});
 841          emit_instruction(ir);
 842       }
 843       if (ir)
 844          ir->set_flag(alu_last_instr);
 845    }
 846
 847    emit_instruction(tex_ir);
 848    return true;
 849 }
 850
 851 bool EmitTexInstruction::get_inputs(const nir_tex_instr& instr, TexInputs &src)
 852 {
 853    sfn_log << SfnLog::tex << "Get Inputs with " << instr.coord_components << " components\n";
 854
 855    unsigned grad_components = instr.coord_components;
 856    if (instr.is_array)
 857       --grad_components;
 858
 859
 860    src.offset = nullptr;
 861    bool retval = true;
 862    for (unsigned i = 0; i < instr.num_srcs; ++i) {
 863       switch (instr.src[i].src_type) {
 864       case nir_tex_src_bias:
 865          src.bias = from_nir(instr.src[i], 0);
 866          break;
 867
 868       case nir_tex_src_coord: {
 869          src.coord = vec_from_nir_with_fetch_constant(instr.src[i].src,
 870                                                       (1 << instr.coord_components) - 1,
 871          {0,1,2,3});
 872       } break;
 873       case nir_tex_src_comparator:
 874          src.comperator = from_nir(instr.src[i], 0);
 875          break;
 876       case nir_tex_src_ddx: {
 877          sfn_log << SfnLog::tex << "Get DDX ";
 878          src.ddx = vec_from_nir_with_fetch_constant(instr.src[i].src,
 879                                                     (1 << grad_components) - 1,
 880                                                     swizzle_from_comps(grad_components));
 881          sfn_log << SfnLog::tex << src.ddx << "\n";
 882       } break;
 883       case nir_tex_src_ddy:{
 884          sfn_log << SfnLog::tex << "Get DDY ";
 885          src.ddy = vec_from_nir_with_fetch_constant(instr.src[i].src,
 886                                                     (1 << grad_components) - 1,
 887                                                     swizzle_from_comps(grad_components));
 888          sfn_log << SfnLog::tex << src.ddy << "\n";
 889       }  break;
 890       case nir_tex_src_lod:
 891          src.lod = from_nir_with_fetch_constant(instr.src[i].src, 0);
 892          break;
 893       case nir_tex_src_offset:
 894          sfn_log << SfnLog::tex << "  -- Find offset\n";
 895          src.offset = &instr.src[i].src;
 896          break;
 897       case nir_tex_src_sampler_deref:
 898          src.sampler_deref = get_deref_location(instr.src[i].src);
 899          break;
 900       case nir_tex_src_texture_deref:
 901          src.texture_deref = get_deref_location(instr.src[i].src);
 902          break;
 903       case nir_tex_src_ms_index:
 904          src.ms_index = from_nir(instr.src[i], 0);
 905          break;
 906       case nir_tex_src_texture_offset:
 907          src.texture_offset = from_nir(instr.src[i], 0);
 908          break;
 909       case nir_tex_src_sampler_offset:
 910          src.sampler_offset = from_nir(instr.src[i], 0);
 911          break;
 912       case nir_tex_src_plane:
 913       case nir_tex_src_projector:
 914       case nir_tex_src_min_lod:
 915       case nir_tex_src_ms_mcs:
 916       default:
 917          sfn_log << SfnLog::tex << "Texture source type " <<  instr.src[i].src_type << " not supported\n";
 918          retval = false;
 919       }
 920    }
 921    return retval;
 922 }
 923
 924 GPRVector EmitTexInstruction::make_dest(nir_tex_instr& instr)
 925 {
 926    int num_dest_components = instr.dest.is_ssa ? instr.dest.ssa.num_components :
 927                                                  instr.dest.reg.reg->num_components;
 928    std::array<PValue,4> dst_elms;
 929    for (uint16_t i = 0; i < 4; ++i)
 930       dst_elms[i] = from_nir(instr.dest, (i < num_dest_components) ? i : 7);
 931    return GPRVector(dst_elms);
 932 }
 933
 934
 935 GPRVector EmitTexInstruction::make_dest(nir_tex_instr& instr,
 936                                         const std::array<int, 4>& swizzle)
 937 {
 938    int num_dest_components = instr.dest.is_ssa ? instr.dest.ssa.num_components :
 939                                                  instr.dest.reg.reg->num_components;
 940    std::array<PValue,4> dst_elms;
 941    for (uint16_t i = 0; i < 4; ++i) {
 942       int k = swizzle[i];
 943       dst_elms[i] = from_nir(instr.dest, (k < num_dest_components) ? k : 7);
 944    }
 945    return GPRVector(dst_elms);
 946 }
 947
 948 void EmitTexInstruction::set_rect_coordinate_flags(nir_tex_instr* instr,
 949                                                    TexInstruction* ir) const
 950 {
 951    if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
 952       ir->set_flag(TexInstruction::x_unnormalized);
 953       ir->set_flag(TexInstruction::y_unnormalized);
 954    }
 955 }
 956
 957 void EmitTexInstruction::set_offsets(TexInstruction* ir, nir_src *offset)
 958 {
 959    if (!offset)
 960       return;
 961
 962    assert(offset->is_ssa);
 963    auto literal = get_literal_register(*offset);
 964    assert(literal);
 965
 966    for (int i = 0; i < offset->ssa->num_components; ++i) {
 967       ir->set_offset(i, literal->value[i].i32);
 968    }
 969 }
 970
 971 void EmitTexInstruction::handle_array_index(const nir_tex_instr& instr, const GPRVector& src, TexInstruction *ir)
 972 {
 973    int src_idx = instr.sampler_dim == GLSL_SAMPLER_DIM_1D ? 1 : 2;
 974    emit_instruction(new AluInstruction(op1_rndne, src.reg_i(2), src.reg_i(src_idx),
 975                                        {alu_last_instr, alu_write}));
 976    ir->set_flag(TexInstruction::z_unnormalized);
 977 }
 978
 979 EmitTexInstruction::SamplerId
 980 EmitTexInstruction::get_samplerr_id(int sampler_id, const nir_variable *deref)
 981 {
 982    EmitTexInstruction::SamplerId result = {sampler_id, false};
 983
 984    if (deref) {
 985       assert(glsl_type_is_sampler(deref->type));
 986       result.id = deref->data.binding;
 987    }
 988    return result;
 989 }
 990
 991 EmitTexInstruction::TexInputs::TexInputs():
 992    sampler_deref(nullptr),
 993    texture_deref(nullptr),
 994    offset(nullptr)
 995 {
 996 }
 997
 998 }