r600/sfn: Fix using the result of a fetch instruction in next fetch
[mesa.git] / src / gallium / drivers / r600 / sfn / sfn_instruction_gds.cpp
1 /* -*- mesa-c++ -*-
2 *
3 * Copyright (c) 2019 Collabora LTD
4 *
5 * Author: Gert Wollny <gert.wollny@collabora.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "sfn_instruction_gds.h"
28 #include "sfn_liverange.h"
29
30 namespace r600 {
31
32 GDSInstr::GDSInstr(ESDOp op, const GPRVector& dest, const PValue& value,
33 const PValue& value2, const PValue& uav_id, int uav_base):
34 Instruction(gds),
35 m_op(op),
36 m_src(value),
37 m_src2(value2),
38 m_dest(dest),
39 m_dest_swizzle({PIPE_SWIZZLE_X,7,7,7}),
40 m_src_swizzle({PIPE_SWIZZLE_0, PIPE_SWIZZLE_X, 7}),
41 m_buffer_index_mode(bim_none),
42 m_uav_id(uav_id),
43 m_uav_base(uav_base),
44 m_flags(0)
45 {
46 add_remappable_src_value(&m_src);
47 add_remappable_src_value(&m_uav_id);
48 add_remappable_dst_value(&m_dest);
49 }
50
51 GDSInstr::GDSInstr(ESDOp op, const GPRVector& dest, const PValue& value,
52 const PValue& uav_id, int uav_base):
53 GDSInstr(op, dest, value, PValue(), uav_id, uav_base)
54 {
55 }
56
57 GDSInstr::GDSInstr(ESDOp op, const GPRVector& dest,
58 const PValue& uav_id, int uav_base):
59 GDSInstr(op, dest, PValue(), PValue(), uav_id, uav_base)
60 {
61 m_src_swizzle[1] = PIPE_SWIZZLE_1;
62 }
63
64 bool GDSInstr::is_equal_to(UNUSED const Instruction& lhs) const
65 {
66 return false;
67 }
68
69 void GDSInstr::do_print(std::ostream& os) const
70 {
71 const char *swz = "xyzw01?_";
72 os << lds_ops.at(m_op).name << " R" << m_dest.sel() << ".";
73 for (int i = 0; i < 4; ++i) {
74 os << swz[m_dest_swizzle[i]];
75 }
76 if (m_src)
77 os << " " << *m_src;
78
79 os << " UAV:" << *m_uav_id;
80 }
81
82 RatInstruction::RatInstruction(ECFOpCode cf_opcode, ERatOp rat_op,
83 const GPRVector& data, const GPRVector& index,
84 int rat_id, const PValue& rat_id_offset,
85 int burst_count, int comp_mask, int element_size, bool ack):
86 Instruction(rat),
87 m_cf_opcode(cf_opcode),
88 m_rat_op(rat_op),
89 m_data(data),
90 m_index(index),
91 m_rat_id(rat_id),
92 m_rat_id_offset(rat_id_offset),
93 m_burst_count(burst_count),
94 m_comp_mask(comp_mask),
95 m_element_size(element_size),
96 m_need_ack(ack)
97 {
98 add_remappable_src_value(&m_data);
99 add_remappable_src_value(&m_rat_id_offset);
100 add_remappable_src_value(&m_index);
101 }
102
103 bool RatInstruction::is_equal_to(UNUSED const Instruction& lhs) const
104 {
105 return false;
106 }
107
108 void RatInstruction::do_print(std::ostream& os) const
109 {
110 os << "MEM_RAT RAT(" << m_rat_id;
111 if (m_rat_id_offset)
112 os << "+" << *m_rat_id_offset;
113 os << ") @" << m_index << " OP:" << m_rat_op << " " << m_data;
114 os << " BC:" << m_burst_count
115 << " MASK:" << m_comp_mask
116 << " ES:" << m_element_size;
117 if (m_need_ack)
118 os << " ACK";
119 }
120
121 RatInstruction::ERatOp RatInstruction::opcode(nir_intrinsic_op opcode)
122 {
123 switch (opcode) {
124 case nir_intrinsic_ssbo_atomic_add:
125 return ADD_RTN;
126 case nir_intrinsic_ssbo_atomic_and:
127 return AND_RTN;
128 case nir_intrinsic_ssbo_atomic_exchange:
129 return XCHG_RTN;
130 case nir_intrinsic_ssbo_atomic_umax:
131 return MAX_UINT_RTN;
132 case nir_intrinsic_ssbo_atomic_umin:
133 return MIN_UINT_RTN;
134 case nir_intrinsic_ssbo_atomic_imax:
135 return MAX_INT_RTN;
136 case nir_intrinsic_ssbo_atomic_imin:
137 return MIN_INT_RTN;
138 case nir_intrinsic_ssbo_atomic_xor:
139 return XOR_RTN;
140 default:
141 return UNSUPPORTED;
142 }
143 }
144
145 }