3 * Copyright (c) 2018 Collabora LTD
5 * Author: Gert Wollny <gert.wollny@collabora.com>
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "../r600_pipe.h"
28 #include "../r600_shader.h"
29 #include "sfn_shader_vertex.h"
31 #include "sfn_shader_compute.h"
32 #include "sfn_shader_fragment.h"
33 #include "sfn_shader_geometry.h"
34 #include "sfn_liverange.h"
35 #include "sfn_ir_to_assembly.h"
37 #include "sfn_instruction_misc.h"
38 #include "sfn_instruction_fetch.h"
39 #include "sfn_instruction_lds.h"
43 #define ENABLE_DEBUG 1
46 #define DEBUG_SFN(X) \
59 ShaderFromNirProcessor::ShaderFromNirProcessor(pipe_shader_type ptype
,
60 r600_pipe_shader_selector
& sel
,
61 r600_shader
&sh_info
, int scratch_size
,
62 enum chip_class chip_class
):
63 m_processor_type(ptype
),
66 m_export_output(0, -1),
68 m_chip_class(chip_class
),
72 m_pending_else(nullptr),
73 m_scratch_size(scratch_size
),
74 m_next_hwatomic_loc(0),
77 m_sh_info
.processor_type
= ptype
;
81 ShaderFromNirProcessor::~ShaderFromNirProcessor()
85 bool ShaderFromNirProcessor::scan_instruction(nir_instr
*instr
)
87 switch (instr
->type
) {
88 case nir_instr_type_tex
: {
89 nir_tex_instr
*t
= nir_instr_as_tex(instr
);
90 if (t
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
91 sh_info().uses_tex_buffers
= true;
97 return scan_sysvalue_access(instr
);
100 enum chip_class
ShaderFromNirProcessor::get_chip_class(void) const
105 bool ShaderFromNirProcessor::allocate_reserved_registers()
107 bool retval
= do_allocate_reserved_registers();
111 static void remap_shader_info(r600_shader
& sh_info
,
112 std::vector
<rename_reg_pair
>& map
,
113 UNUSED ValueMap
& values
)
115 for (unsigned i
= 0; i
< sh_info
.ninput
; ++i
) {
116 sfn_log
<< SfnLog::merge
<< "Input " << i
<< " gpr:" << sh_info
.input
[i
].gpr
117 << " of map.size()\n";
119 assert(sh_info
.input
[i
].gpr
< map
.size());
120 auto new_index
= map
[sh_info
.input
[i
].gpr
];
122 sh_info
.input
[i
].gpr
= new_index
.new_reg
;
123 map
[sh_info
.input
[i
].gpr
].used
= true;
126 for (unsigned i
= 0; i
< sh_info
.noutput
; ++i
) {
127 assert(sh_info
.output
[i
].gpr
< map
.size());
128 auto new_index
= map
[sh_info
.output
[i
].gpr
];
130 sh_info
.output
[i
].gpr
= new_index
.new_reg
;
131 map
[sh_info
.output
[i
].gpr
].used
= true;
135 void ShaderFromNirProcessor::remap_registers()
137 // register renumbering
138 auto rc
= register_count();
142 std::vector
<register_live_range
> register_live_ranges(rc
);
144 auto temp_register_map
= get_temp_registers();
146 Shader sh
{m_output
, temp_register_map
};
147 LiverangeEvaluator().run(sh
, register_live_ranges
);
148 auto register_map
= get_temp_registers_remapping(register_live_ranges
);
150 sfn_log
<< SfnLog::merge
<< "=========Mapping===========\n";
151 for (size_t i
= 0; i
< register_map
.size(); ++i
)
152 if (register_map
[i
].valid
)
153 sfn_log
<< SfnLog::merge
<< "Map:" << i
<< " -> " << register_map
[i
].new_reg
<< "\n";
155 ValueRemapper
vmap0(register_map
, temp_register_map
);
156 for (auto& block
: m_output
)
157 block
.remap_registers(vmap0
);
159 remap_shader_info(m_sh_info
, register_map
, temp_register_map
);
161 /* Mark inputs as used registers, these registers should no be remapped */
162 for (auto& v
: sh
.m_temp
) {
163 if (v
.second
->type() == Value::gpr
) {
164 const auto& g
= static_cast<const GPRValue
&>(*v
.second
);
166 register_map
[g
.sel()].used
= true;
171 for (auto& i
: register_map
) {
174 i
.new_reg
= new_index
++;
177 ValueRemapper
vmap1(register_map
, temp_register_map
);
178 for (auto& ir
: m_output
)
179 ir
.remap_registers(vmap1
);
181 remap_shader_info(m_sh_info
, register_map
, temp_register_map
);
184 bool ShaderFromNirProcessor::process_uniforms(nir_variable
*uniform
)
186 // m_uniform_type_map
187 m_uniform_type_map
[uniform
->data
.location
] = uniform
->type
;
189 if (uniform
->type
->contains_atomic()) {
190 int natomics
= uniform
->type
->atomic_size() / ATOMIC_COUNTER_SIZE
;
191 sh_info().nhwatomic
+= natomics
;
193 if (uniform
->type
->is_array())
194 sh_info().indirect_files
|= 1 << TGSI_FILE_HW_ATOMIC
;
196 sh_info().uses_atomics
= 1;
198 struct r600_shader_atomic
& atom
= sh_info().atomics
[sh_info().nhwatomic_ranges
];
199 ++sh_info().nhwatomic_ranges
;
200 atom
.buffer_id
= uniform
->data
.binding
;
201 atom
.hw_idx
= m_next_hwatomic_loc
;
202 atom
.start
= m_next_hwatomic_loc
;
203 atom
.end
= atom
.start
+ natomics
- 1;
204 m_next_hwatomic_loc
= atom
.end
+ 1;
205 //atom.array_id = uniform->type->is_array() ? 1 : 0;
207 m_sel
.info
.file_count
[TGSI_FILE_HW_ATOMIC
] += atom
.end
- atom
.start
+ 1;
209 sfn_log
<< SfnLog::io
<< "HW_ATOMIC file count: "
210 << m_sel
.info
.file_count
[TGSI_FILE_HW_ATOMIC
] << "\n";
213 if (uniform
->type
->is_image() || uniform
->data
.mode
== nir_var_mem_ssbo
) {
214 sh_info().uses_images
= 1;
220 bool ShaderFromNirProcessor::process_inputs(nir_variable
*input
)
222 return do_process_inputs(input
);
225 bool ShaderFromNirProcessor::process_outputs(nir_variable
*output
)
227 return do_process_outputs(output
);
230 void ShaderFromNirProcessor::add_array_deref(nir_deref_instr
*instr
)
232 nir_variable
*var
= nir_deref_instr_get_variable(instr
);
234 assert(instr
->mode
== nir_var_function_temp
);
235 assert(glsl_type_is_array(var
->type
));
237 // add an alias for the index to the register(s);
242 void ShaderFromNirProcessor::set_var_address(nir_deref_instr
*instr
)
244 auto& dest
= instr
->dest
;
245 unsigned index
= dest
.is_ssa
? dest
.ssa
.index
: dest
.reg
.reg
->index
;
246 m_var_mode
[instr
->var
] = instr
->mode
;
247 m_var_derefs
[index
] = instr
->var
;
249 sfn_log
<< SfnLog::io
<< "Add var deref:" << index
250 << " with DDL:" << instr
->var
->data
.driver_location
<< "\n";
253 void ShaderFromNirProcessor::evaluate_spi_sid(r600_shader_io
& io
)
256 case TGSI_SEMANTIC_POSITION
:
257 case TGSI_SEMANTIC_PSIZE
:
258 case TGSI_SEMANTIC_EDGEFLAG
:
259 case TGSI_SEMANTIC_FACE
:
260 case TGSI_SEMANTIC_SAMPLEMASK
:
261 case TGSI_SEMANTIC_CLIPVERTEX
:
264 case TGSI_SEMANTIC_GENERIC
:
265 case TGSI_SEMANTIC_TEXCOORD
:
266 case TGSI_SEMANTIC_PCOORD
:
267 io
.spi_sid
= io
.sid
+ 1;
270 /* For non-generic params - pack name and sid into 8 bits */
271 io
.spi_sid
= (0x80 | (io
.name
<< 3) | io
.sid
) + 1;
275 const nir_variable
*ShaderFromNirProcessor::get_deref_location(const nir_src
& src
) const
277 unsigned index
= src
.is_ssa
? src
.ssa
->index
: src
.reg
.reg
->index
;
279 sfn_log
<< SfnLog::io
<< "Search for deref:" << index
<< "\n";
281 auto v
= m_var_derefs
.find(index
);
282 if (v
!= m_var_derefs
.end())
285 fprintf(stderr
, "R600: could not find deref with index %d\n", index
);
289 /*nir_deref_instr *deref = nir_instr_as_deref(src.ssa->parent_instr);
290 return nir_deref_instr_get_variable(deref); */
293 bool ShaderFromNirProcessor::emit_tex_instruction(nir_instr
* instr
)
295 return m_tex_instr
.emit(instr
);
298 void ShaderFromNirProcessor::emit_instruction(Instruction
*ir
)
300 if (m_pending_else
) {
302 m_output
.back().emit(PInstruction(m_pending_else
));
304 m_pending_else
= nullptr;
307 r600::sfn_log
<< SfnLog::instr
<< " as '" << *ir
<< "'\n";
308 if (m_output
.empty())
311 m_output
.back().emit(Instruction::Pointer(ir
));
314 void ShaderFromNirProcessor::emit_shader_start()
316 /* placeholder, may become an abstract method */
319 bool ShaderFromNirProcessor::emit_jump_instruction(nir_jump_instr
*instr
)
321 switch (instr
->type
) {
322 case nir_jump_break
: {
323 auto b
= new LoopBreakInstruction();
327 case nir_jump_continue
: {
328 auto b
= new LoopContInstruction();
333 nir_instr
*i
= reinterpret_cast<nir_instr
*>(instr
);
334 sfn_log
<< SfnLog::err
<< "Jump instrunction " << *i
<< " not supported\n";
341 bool ShaderFromNirProcessor::emit_alu_instruction(nir_instr
* instr
)
343 return m_alu_instr
.emit(instr
);
346 bool ShaderFromNirProcessor::emit_deref_instruction_override(UNUSED nir_deref_instr
* instr
)
351 bool ShaderFromNirProcessor::emit_loop_start(int loop_id
)
353 LoopBeginInstruction
*loop
= new LoopBeginInstruction();
354 emit_instruction(loop
);
355 m_loop_begin_block_map
[loop_id
] = loop
;
359 bool ShaderFromNirProcessor::emit_loop_end(int loop_id
)
361 auto start
= m_loop_begin_block_map
.find(loop_id
);
362 if (start
== m_loop_begin_block_map
.end()) {
363 sfn_log
<< SfnLog::err
<< "End loop: Loop start for "
364 << loop_id
<< " not found\n";
369 m_output
.push_back(InstructionBlock(m_nesting_depth
, m_block_number
));
370 LoopEndInstruction
*loop
= new LoopEndInstruction(start
->second
);
371 emit_instruction(loop
);
373 m_loop_begin_block_map
.erase(start
);
377 bool ShaderFromNirProcessor::emit_if_start(int if_id
, nir_if
*if_stmt
)
380 auto value
= from_nir(if_stmt
->condition
, 0, 0);
381 AluInstruction
*pred
= new AluInstruction(op2_pred_setne_int
, PValue(new GPRValue(0,0)),
382 value
, Value::zero
, EmitInstruction::last
);
383 pred
->set_flag(alu_update_exec
);
384 pred
->set_flag(alu_update_pred
);
385 pred
->set_cf_type(cf_alu_push_before
);
389 IfInstruction
*ir
= new IfInstruction(pred
);
390 emit_instruction(ir
);
391 assert(m_if_block_start_map
.find(if_id
) == m_if_block_start_map
.end());
392 m_if_block_start_map
[if_id
] = ir
;
396 bool ShaderFromNirProcessor::emit_else_start(int if_id
)
398 auto iif
= m_if_block_start_map
.find(if_id
);
399 if (iif
== m_if_block_start_map
.end()) {
400 std::cerr
<< "Error: ELSE branch " << if_id
<< " without starting conditional branch\n";
404 if (iif
->second
->type() != Instruction::cond_if
) {
405 std::cerr
<< "Error: ELSE branch " << if_id
<< " not started by an IF branch\n";
408 IfInstruction
*if_instr
= static_cast<IfInstruction
*>(iif
->second
);
409 ElseInstruction
*ir
= new ElseInstruction(if_instr
);
410 m_if_block_start_map
[if_id
] = ir
;
416 bool ShaderFromNirProcessor::emit_ifelse_end(int if_id
)
418 auto ifelse
= m_if_block_start_map
.find(if_id
);
419 if (ifelse
== m_if_block_start_map
.end()) {
420 std::cerr
<< "Error: ENDIF " << if_id
<< " without THEN or ELSE branch\n";
424 if (ifelse
->second
->type() != Instruction::cond_if
&&
425 ifelse
->second
->type() != Instruction::cond_else
) {
426 std::cerr
<< "Error: ENDIF " << if_id
<< " doesn't close an IF or ELSE branch\n";
429 /* Clear pending else, if the else branch was empty, non will be emitted */
431 m_pending_else
= nullptr;
434 IfElseEndInstruction
*ir
= new IfElseEndInstruction();
435 emit_instruction(ir
);
440 bool ShaderFromNirProcessor::emit_load_tcs_param_base(nir_intrinsic_instr
* instr
, int offset
)
442 PValue src
= get_temp_register();
443 emit_instruction(new AluInstruction(op1_mov
, src
, Value::zero
, {alu_write
, alu_last_instr
}));
445 GPRVector dest
= vec_from_nir(instr
->dest
, instr
->num_components
);
446 emit_instruction(new FetchTCSIOParam(dest
, src
, offset
));
452 bool ShaderFromNirProcessor::emit_load_local_shared(nir_intrinsic_instr
* instr
)
454 auto address
= varvec_from_nir(instr
->src
[0], instr
->num_components
);
455 auto dest_value
= varvec_from_nir(instr
->dest
, instr
->num_components
);
457 emit_instruction(new LDSReadInstruction(address
, dest_value
));
461 bool ShaderFromNirProcessor::emit_store_local_shared(nir_intrinsic_instr
* instr
)
463 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
465 auto address
= from_nir(instr
->src
[1], 0);
466 int swizzle_base
= (write_mask
& 0x3) ? 0 : 2;
467 write_mask
|= write_mask
>> 2;
469 auto value
= from_nir(instr
->src
[0], swizzle_base
);
470 if (!(write_mask
& 2)) {
471 emit_instruction(new LDSWriteInstruction(address
, 0, value
));
473 auto value1
= from_nir(instr
->src
[0], swizzle_base
+ 1);
474 emit_instruction(new LDSWriteInstruction(address
, 0, value
, value1
));
480 bool ShaderFromNirProcessor::emit_intrinsic_instruction(nir_intrinsic_instr
* instr
)
482 r600::sfn_log
<< SfnLog::instr
<< "emit '"
483 << *reinterpret_cast<nir_instr
*>(instr
)
484 << "' (" << __func__
<< ")\n";
486 if (emit_intrinsic_instruction_override(instr
))
489 switch (instr
->intrinsic
) {
490 case nir_intrinsic_load_deref
: {
491 auto var
= get_deref_location(instr
->src
[0]);
494 auto mode_helper
= m_var_mode
.find(var
);
495 if (mode_helper
== m_var_mode
.end()) {
496 cerr
<< "r600-nir: variable '" << var
->name
<< "' not found\n";
499 switch (mode_helper
->second
) {
500 case nir_var_shader_in
:
501 return emit_load_input_deref(var
, instr
);
502 case nir_var_function_temp
:
503 return emit_load_function_temp(var
, instr
);
505 cerr
<< "r600-nir: Unsupported mode" << mode_helper
->second
506 << "for src variable\n";
510 case nir_intrinsic_store_scratch
:
511 return emit_store_scratch(instr
);
512 case nir_intrinsic_load_scratch
:
513 return emit_load_scratch(instr
);
514 case nir_intrinsic_store_deref
:
515 return emit_store_deref(instr
);
516 case nir_intrinsic_load_uniform
:
517 return reserve_uniform(instr
);
518 case nir_intrinsic_discard
:
519 case nir_intrinsic_discard_if
:
520 return emit_discard_if(instr
);
521 case nir_intrinsic_load_ubo_r600
:
522 return emit_load_ubo(instr
);
523 case nir_intrinsic_atomic_counter_add
:
524 case nir_intrinsic_atomic_counter_and
:
525 case nir_intrinsic_atomic_counter_exchange
:
526 case nir_intrinsic_atomic_counter_max
:
527 case nir_intrinsic_atomic_counter_min
:
528 case nir_intrinsic_atomic_counter_or
:
529 case nir_intrinsic_atomic_counter_xor
:
530 case nir_intrinsic_atomic_counter_comp_swap
:
531 case nir_intrinsic_atomic_counter_read
:
532 case nir_intrinsic_atomic_counter_post_dec
:
533 case nir_intrinsic_atomic_counter_inc
:
534 case nir_intrinsic_atomic_counter_pre_dec
:
535 case nir_intrinsic_store_ssbo
:
536 m_sel
.info
.writes_memory
= true;
538 case nir_intrinsic_load_ssbo
:
539 return m_ssbo_instr
.emit(&instr
->instr
);
541 case nir_intrinsic_copy_deref
:
542 case nir_intrinsic_load_constant
:
543 case nir_intrinsic_load_input
:
544 case nir_intrinsic_store_output
:
545 case nir_intrinsic_load_tcs_in_param_base_r600
:
546 return emit_load_tcs_param_base(instr
, 0);
547 case nir_intrinsic_load_tcs_out_param_base_r600
:
548 return emit_load_tcs_param_base(instr
, 16);
549 case nir_intrinsic_load_local_shared_r600
:
550 return emit_load_local_shared(instr
);
551 case nir_intrinsic_store_local_shared_r600
:
552 return emit_store_local_shared(instr
);
553 case nir_intrinsic_control_barrier
:
554 case nir_intrinsic_memory_barrier_tcs_patch
:
555 return emit_barrier(instr
);
558 fprintf(stderr
, "r600-nir: Unsupported intrinsic %d\n", instr
->intrinsic
);
564 bool ShaderFromNirProcessor::emit_intrinsic_instruction_override(UNUSED nir_intrinsic_instr
* instr
)
570 ShaderFromNirProcessor::emit_load_function_temp(UNUSED
const nir_variable
*var
, UNUSED nir_intrinsic_instr
*instr
)
575 bool ShaderFromNirProcessor::emit_barrier(UNUSED nir_intrinsic_instr
* instr
)
577 AluInstruction
*ir
= new AluInstruction(op0_group_barrier
);
578 ir
->set_flag(alu_last_instr
);
579 emit_instruction(ir
);
584 bool ShaderFromNirProcessor::load_preloaded_value(const nir_dest
& dest
, int chan
, PValue value
, bool as_last
)
587 auto ir
= new AluInstruction(op1_mov
, from_nir(dest
, 0), value
, {alu_write
});
589 ir
->set_flag(alu_last_instr
);
590 emit_instruction(ir
);
592 inject_register(dest
.ssa
.index
, chan
, value
, true);
597 bool ShaderFromNirProcessor::emit_store_scratch(nir_intrinsic_instr
* instr
)
599 PValue address
= from_nir(instr
->src
[1], 0, 0);
601 auto value
= vec_from_nir_with_fetch_constant(instr
->src
[0], (1 << instr
->num_components
) - 1,
602 swizzle_from_comps(instr
->num_components
));
604 int writemask
= nir_intrinsic_write_mask(instr
);
605 int align
= nir_intrinsic_align_mul(instr
);
606 int align_offset
= nir_intrinsic_align_offset(instr
);
608 WriteScratchInstruction
*ir
= nullptr;
609 if (address
->type() == Value::literal
) {
610 const auto& lv
= static_cast<const LiteralValue
&>(*address
);
611 ir
= new WriteScratchInstruction(lv
.value(), value
, align
, align_offset
, writemask
);
613 address
= from_nir_with_fetch_constant(instr
->src
[1], 0);
614 ir
= new WriteScratchInstruction(address
, value
, align
, align_offset
,
615 writemask
, m_scratch_size
);
617 emit_instruction(ir
);
618 sh_info().needs_scratch_space
= 1;
622 bool ShaderFromNirProcessor::emit_load_scratch(nir_intrinsic_instr
* instr
)
624 PValue address
= from_nir_with_fetch_constant(instr
->src
[0], 0);
625 std::array
<PValue
, 4> dst_val
;
626 for (int i
= 0; i
< 4; ++i
)
627 dst_val
[i
] = from_nir(instr
->dest
, i
< instr
->num_components
? i
: 7);
629 GPRVector
dst(dst_val
);
630 auto ir
= new LoadFromScratch(dst
, address
, m_scratch_size
);
631 ir
->prelude_append(new WaitAck(0));
632 emit_instruction(ir
);
633 sh_info().needs_scratch_space
= 1;
637 GPRVector
ShaderFromNirProcessor::vec_from_nir_with_fetch_constant(const nir_src
& src
,
639 const GPRVector::Swizzle
& swizzle
,
642 bool use_same
= true;
645 for (int i
= 0; i
< 4 && use_same
; ++i
) {
646 if ((1 << i
) & mask
) {
647 if (swizzle
[i
] < 4) {
648 v
[i
] = from_nir(src
, swizzle
[i
]);
650 if (v
[i
]->type() != Value::gpr
)
652 if (match
&& (v
[i
]->chan() != swizzle
[i
]))
660 while (!v
[i
] && i
< 4) ++i
;
663 unsigned sel
= v
[i
]->sel();
664 for (i
= 0; i
< 4 && use_same
; ++i
) {
666 v
[i
] = PValue(new GPRValue(sel
, swizzle
[i
]));
668 use_same
&= v
[i
]->sel() == sel
;
673 AluInstruction
*ir
= nullptr;
674 int sel
= allocate_temp_register();
675 for (int i
= 0; i
< 4; ++i
) {
676 v
[i
] = PValue(new GPRValue(sel
, swizzle
[i
]));
677 if (swizzle
[i
] < 4 && (mask
& (1 << i
))) {
678 ir
= new AluInstruction(op1_mov
, v
[i
], from_nir(src
, swizzle
[i
]),
679 EmitInstruction::write
);
680 emit_instruction(ir
);
684 ir
->set_flag(alu_last_instr
);
686 return GPRVector(v
);;
689 bool ShaderFromNirProcessor::emit_load_ubo(nir_intrinsic_instr
* instr
)
691 nir_src
& src0
= instr
->src
[0];
692 nir_src
& src1
= instr
->src
[1];
694 int sel_bufid_reg
= src0
.is_ssa
? src0
.ssa
->index
: src0
.reg
.reg
->index
;
695 const nir_load_const_instr
* literal0
= get_literal_constant(sel_bufid_reg
);
697 int ofs_reg
= src1
.is_ssa
? src1
.ssa
->index
: src1
.reg
.reg
->index
;
698 const nir_load_const_instr
* literal1
= get_literal_constant(ofs_reg
);
701 uint bufid
= literal0
->value
[0].u32
;
702 uint buf_ofs
= literal1
->value
[0].u32
>> 4;
703 int buf_cmp
= ((literal1
->value
[0].u32
>> 2) & 3);
704 AluInstruction
*ir
= nullptr;
705 for (int i
= 0; i
< instr
->num_components
; ++i
) {
706 int cmp
= buf_cmp
+ i
;
708 auto u
= PValue(new UniformValue(512 + buf_ofs
, cmp
, bufid
+ 1));
709 if (instr
->dest
.is_ssa
)
710 add_uniform((instr
->dest
.ssa
.index
<< 2) + i
, u
);
712 ir
= new AluInstruction(op1_mov
, from_nir(instr
->dest
, i
), u
, {alu_write
});
713 emit_instruction(ir
);
717 ir
->set_flag(alu_last_instr
);
721 /* literal0 is lost ...*/
722 return load_uniform_indirect(instr
, from_nir(instr
->src
[1], 0, 0), 0, literal0
->value
[0].u32
+ 1);
725 /* TODO: This can also be solved by using the CF indes on the ALU block, and
726 * this would probably make sense when there are more then one loads with
727 * the same buffer ID. */
728 PValue bufid
= from_nir(instr
->src
[0], 0, 0);
729 PValue addr
= from_nir_with_fetch_constant(instr
->src
[1], 0);
731 for (int i
= 0; i
< 4; ++i
)
732 trgt
.set_reg_i(i
, from_nir(instr
->dest
, i
));
734 auto ir
= new FetchInstruction(vc_fetch
, no_index_offset
, trgt
, addr
, 0,
737 emit_instruction(ir
);
738 for (int i
= 0; i
< instr
->num_components
; ++i
) {
739 add_uniform((instr
->dest
.ssa
.index
<< 2) + i
, trgt
.reg_i(i
));
741 m_sh_info
.indirect_files
|= 1 << TGSI_FILE_CONSTANT
;
747 bool ShaderFromNirProcessor::emit_discard_if(nir_intrinsic_instr
* instr
)
749 r600::sfn_log
<< SfnLog::instr
<< "emit '"
750 << *reinterpret_cast<nir_instr
*>(instr
)
751 << "' (" << __func__
<< ")\n";
753 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
754 emit_instruction(new AluInstruction(op2_killne_int
, PValue(new GPRValue(0,0)),
755 {from_nir(instr
->src
[0], 0, 0), Value::zero
}, {alu_last_instr
}));
758 emit_instruction(new AluInstruction(op2_kille
, PValue(new GPRValue(0,0)),
759 {Value::zero
, Value::zero
}, {alu_last_instr
}));
761 m_sh_info
.uses_kill
= 1;
765 bool ShaderFromNirProcessor::emit_load_input_deref(const nir_variable
*var
,
766 nir_intrinsic_instr
* instr
)
768 return do_emit_load_deref(var
, instr
);
771 bool ShaderFromNirProcessor::reserve_uniform(nir_intrinsic_instr
* instr
)
773 r600::sfn_log
<< SfnLog::instr
<< __func__
<< ": emit '"
774 << *reinterpret_cast<nir_instr
*>(instr
)
778 /* If the target register is a SSA register and the loading is not
779 * indirect then we can do lazy loading, i.e. the uniform value can
780 * be used directly. Otherwise we have to load the data for real
784 /* Try to find the literal that defines the array index */
785 const nir_load_const_instr
* literal
= nullptr;
786 if (instr
->src
[0].is_ssa
)
787 literal
= get_literal_constant(instr
->src
[0].ssa
->index
);
789 int base
= nir_intrinsic_base(instr
);
791 AluInstruction
*ir
= nullptr;
793 for (int i
= 0; i
< instr
->num_components
; ++i
) {
794 PValue u
= PValue(new UniformValue(512 + literal
->value
[0].u32
+ base
, i
));
795 sfn_log
<< SfnLog::io
<< "uniform "
796 << instr
->dest
.ssa
.index
<< " const["<< i
<< "]: "<< instr
->const_index
[i
] << "\n";
798 if (instr
->dest
.is_ssa
)
799 add_uniform((instr
->dest
.ssa
.index
<< 2) + i
, u
);
801 ir
= new AluInstruction(op1_mov
, from_nir(instr
->dest
, i
),
803 emit_instruction(ir
);
807 ir
->set_flag(alu_last_instr
);
809 PValue addr
= from_nir(instr
->src
[0], 0, 0);
810 return load_uniform_indirect(instr
, addr
, 16 * base
, 0);
815 bool ShaderFromNirProcessor::load_uniform_indirect(nir_intrinsic_instr
* instr
, PValue addr
, int offest
, int bufferid
)
818 std::cerr
<< "r600-nir: don't know how uniform is addressed\n";
823 for (int i
= 0; i
< 4; ++i
)
824 trgt
.set_reg_i(i
, from_nir(instr
->dest
, i
));
826 if (addr
->type() != Value::gpr
) {
827 emit_instruction(op1_mov
, trgt
.reg_i(0), {addr
}, {alu_write
, alu_last_instr
});
828 addr
= trgt
.reg_i(0);
831 /* FIXME: buffer index and index mode are not set correctly */
832 auto ir
= new FetchInstruction(vc_fetch
, no_index_offset
, trgt
, addr
, offest
,
833 bufferid
, PValue(), bim_none
);
834 emit_instruction(ir
);
835 for (int i
= 0; i
< instr
->num_components
; ++i
) {
836 add_uniform((instr
->dest
.ssa
.index
<< 2) + i
, trgt
.reg_i(i
));
838 m_sh_info
.indirect_files
|= 1 << TGSI_FILE_CONSTANT
;
842 AluInstruction
*ShaderFromNirProcessor::emit_load_literal(const nir_load_const_instr
* literal
, const nir_src
& src
, unsigned writemask
)
844 AluInstruction
*ir
= nullptr;
845 for (int i
= 0; i
< literal
->def
.num_components
; ++i
) {
846 if (writemask
& (1 << i
)){
848 switch (literal
->def
.bit_size
) {
851 sfn_log
<< SfnLog::reg
<< "Got literal of bit size 1\n";
852 lsrc
= literal
->value
[i
].b
?
853 PValue(new LiteralValue( 0xffffffff, i
)) :
857 sfn_log
<< SfnLog::reg
<< "Got literal of bit size 32\n";
858 if (literal
->value
[i
].u32
== 0)
860 else if (literal
->value
[i
].u32
== 1)
862 else if (literal
->value
[i
].f32
== 1.0f
)
864 else if (literal
->value
[i
].f32
== 0.5f
)
865 lsrc
= Value::zero_dot_5
;
867 lsrc
= PValue(new LiteralValue(literal
->value
[i
].u32
, i
));
870 sfn_log
<< SfnLog::reg
<< "Got literal of bit size " << literal
->def
.bit_size
871 << " falling back to 32 bit\n";
872 lsrc
= PValue(new LiteralValue(literal
->value
[i
].u32
, i
));
874 ir
= new AluInstruction(op1_mov
, create_register_from_nir_src(src
, i
), lsrc
, EmitInstruction::write
);
876 emit_instruction(ir
);
882 PValue
ShaderFromNirProcessor::from_nir_with_fetch_constant(const nir_src
& src
, unsigned component
)
884 PValue value
= from_nir(src
, component
);
885 if (value
->type() != Value::gpr
&&
886 value
->type() != Value::gpr_vector
&&
887 value
->type() != Value::gpr_array_value
) {
888 PValue retval
= get_temp_register();
889 emit_instruction(new AluInstruction(op1_mov
, retval
, value
,
890 EmitInstruction::last_write
));
896 bool ShaderFromNirProcessor::emit_store_deref(nir_intrinsic_instr
* instr
)
898 auto out_var
= get_deref_location(instr
->src
[0]);
902 return do_emit_store_deref(out_var
, instr
);
905 bool ShaderFromNirProcessor::emit_deref_instruction(nir_deref_instr
* instr
)
907 r600::sfn_log
<< SfnLog::instr
<< __func__
<< ": emit '"
908 << *reinterpret_cast<nir_instr
*>(instr
)
911 /* Give the specific shader type a chance to process this, i.e. Geometry and
912 * tesselation shaders need specialized deref_array, for the other shaders
915 if (emit_deref_instruction_override(instr
))
918 switch (instr
->deref_type
) {
919 case nir_deref_type_var
:
920 set_var_address(instr
);
922 case nir_deref_type_array
:
923 case nir_deref_type_array_wildcard
:
924 case nir_deref_type_struct
:
925 case nir_deref_type_cast
:
927 fprintf(stderr
, "R600: deref type %d not supported\n", instr
->deref_type
);
932 void ShaderFromNirProcessor::load_uniform(const nir_alu_src
&src
)
934 AluInstruction
*ir
= nullptr;
937 assert(src
.src
.is_ssa
);
939 for (int i
= 0; i
< src
.src
.ssa
->num_components
; ++i
) {
940 unsigned uindex
= (src
.src
.ssa
->index
<< 2) + i
;
941 sv
[i
] = uniform(uindex
);
945 for (int i
= 0; i
< src
.src
.ssa
->num_components
; ++i
) {
946 ir
= new AluInstruction(op1_mov
, create_register_from_nir_src(src
.src
, i
), sv
[i
],
947 EmitInstruction::write
);
948 emit_instruction(ir
);
951 ir
->set_flag(alu_last_instr
);
956 bool ShaderFromNirProcessor::emit_instruction(EAluOp opcode
, PValue dest
,
957 std::vector
<PValue
> srcs
,
958 const std::set
<AluModifiers
>& m_flags
)
960 AluInstruction
*ir
= new AluInstruction(opcode
, dest
, srcs
, m_flags
);
961 emit_instruction(ir
);
965 void ShaderFromNirProcessor::add_param_output_reg(int loc
, const GPRVector
*gpr
)
967 m_output_register_map
[loc
] = gpr
;
970 void ShaderFromNirProcessor::emit_export_instruction(WriteoutInstruction
*ir
)
972 r600::sfn_log
<< SfnLog::instr
<< " as '" << *ir
<< "'\n";
973 m_export_output
.emit(PInstruction(ir
));
976 const GPRVector
* ShaderFromNirProcessor::output_register(unsigned location
) const
978 const GPRVector
*retval
= nullptr;
979 auto val
= m_output_register_map
.find(location
);
980 if (val
!= m_output_register_map
.end())
981 retval
= val
->second
;
985 void ShaderFromNirProcessor::set_input(unsigned pos
, PValue var
)
987 r600::sfn_log
<< SfnLog::io
<< "Set input[" << pos
<< "] =" << *var
<< "\n";
991 void ShaderFromNirProcessor::set_output(unsigned pos
, int sel
)
993 r600::sfn_log
<< SfnLog::io
<< "Set output[" << pos
<< "] =" << sel
<< "\n";
994 m_outputs
[pos
] = sel
;
997 void ShaderFromNirProcessor::append_block(int nesting_change
)
999 m_nesting_depth
+= nesting_change
;
1000 m_output
.push_back(InstructionBlock(m_nesting_depth
, m_block_number
++));
1003 void ShaderFromNirProcessor::finalize()
1007 for (auto& i
: m_inputs
)
1008 m_sh_info
.input
[i
.first
].gpr
= i
.second
->sel();
1010 for (auto& i
: m_outputs
)
1011 m_sh_info
.output
[i
.first
].gpr
= i
.second
;
1013 m_output
.push_back(m_export_output
);