3 * Copyright (c) 2018 Collabora LTD
5 * Author: Gert Wollny <gert.wollny@collabora.com>
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "sfn_shader_compute.h"
28 #include "sfn_instruction_fetch.h"
32 ComputeShaderFromNir::ComputeShaderFromNir(r600_pipe_shader
*sh
,
33 r600_pipe_shader_selector
& sel
,
34 UNUSED
const r600_shader_key
& key
,
35 enum chip_class chip_class
):
36 ShaderFromNirProcessor (PIPE_SHADER_COMPUTE
, sel
, sh
->shader
,
37 sh
->scratch_space_needed
, chip_class
),
38 m_reserved_registers(0)
42 bool ComputeShaderFromNir::scan_sysvalue_access(UNUSED nir_instr
*instr
)
46 bool ComputeShaderFromNir::allocate_reserved_registers()
48 int thread_id_sel
= m_reserved_registers
++;
49 int wg_id_sel
= m_reserved_registers
++;
51 for (int i
= 0; i
< 3; ++i
) {
52 auto tmp
= new GPRValue(thread_id_sel
, i
);
54 m_local_invocation_id
[i
] = PValue(tmp
);
55 inject_register(tmp
->sel(), i
, m_local_invocation_id
[i
], false);
57 tmp
= new GPRValue(wg_id_sel
, i
);
59 m_workgroup_id
[i
] = PValue(tmp
);
60 inject_register(tmp
->sel(), i
, m_workgroup_id
[i
], false);
65 bool ComputeShaderFromNir::emit_intrinsic_instruction_override(nir_intrinsic_instr
* instr
)
67 switch (instr
->intrinsic
) {
68 case nir_intrinsic_load_local_invocation_id
:
69 return emit_load_3vec(instr
, m_local_invocation_id
);
70 case nir_intrinsic_load_work_group_id
:
71 return emit_load_3vec(instr
, m_workgroup_id
);
72 case nir_intrinsic_load_num_work_groups
:
73 return emit_load_num_work_groups(instr
);
79 bool ComputeShaderFromNir::emit_load_3vec(nir_intrinsic_instr
* instr
,
80 const std::array
<PValue
,3>& src
)
82 AluInstruction
*ir
= nullptr;
83 for (int i
= 0; i
< 3; ++i
) {
84 ir
= new AluInstruction(op1_mov
, from_nir(instr
->dest
, i
), src
[i
], {alu_write
});
87 ir
->set_flag(alu_last_instr
);
91 bool ComputeShaderFromNir::emit_load_num_work_groups(nir_intrinsic_instr
* instr
)
93 int temp
= allocate_temp_register();
94 PValue
a_zero(new GPRValue(temp
, 1));
95 emit_instruction(new AluInstruction(op1_mov
, a_zero
, Value::zero
, EmitInstruction::last_write
));
97 for (int i
= 0; i
< 3; ++i
)
98 dest
.set_reg_i(i
, from_nir(instr
->dest
, i
));
99 dest
.set_reg_i(3, from_nir(instr
->dest
, 7));
101 auto ir
= new FetchInstruction(vc_fetch
, no_index_offset
,
102 fmt_32_32_32_32
, vtx_nf_int
, vtx_es_none
, a_zero
, dest
, 16,
103 false, 16, R600_BUFFER_INFO_CONST_BUFFER
, 0,
104 bim_none
, false, false, 0, 0, 0, PValue(), {0,1,2,7});
105 ir
->set_flag(vtx_srf_mode
);
106 emit_instruction(ir
);
110 bool ComputeShaderFromNir::do_process_inputs(UNUSED nir_variable
*input
)
115 bool ComputeShaderFromNir::do_process_outputs(UNUSED nir_variable
*output
)
120 bool ComputeShaderFromNir::do_emit_load_deref(UNUSED
const nir_variable
*in_var
,
121 UNUSED nir_intrinsic_instr
* instr
)
126 bool ComputeShaderFromNir::do_emit_store_deref(UNUSED
const nir_variable
*out_var
,
127 UNUSED nir_intrinsic_instr
* instr
)
131 void ComputeShaderFromNir::do_finalize()