radeon/llvm: Fix isEG tablegen predicate
[mesa.git] / src / gallium / drivers / radeon / AMDGPUCodeEmitter.h
1 //===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // CodeEmitter interface for R600 and SI codegen.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef AMDGPUCODEEMITTER_H
15 #define AMDGPUCODEEMITTER_H
16
17 namespace llvm {
18
19 class AMDGPUCodeEmitter {
20 public:
21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
22 virtual uint64_t getMachineOpValue(const MachineInstr &MI,
23 const MachineOperand &MO) const { return 0; }
24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
25 unsigned OpNo) const {
26 return 0;
27 }
28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
29 unsigned OpNo) const {
30 return 0;
31 }
32 virtual uint64_t VOPPostEncode(const MachineInstr &MI,
33 uint64_t Value) const {
34 return Value;
35 }
36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI,
37 unsigned OpNo) const {
38 return 0;
39 }
40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)
41 const {
42 return 0;
43 }
44 };
45
46 } // End namespace llvm
47
48 #endif // AMDGPUCODEEMITTER_H