radeon/llvm: Move lowering of SETCC node to R600ISelLowering
[mesa.git] / src / gallium / drivers / radeon / AMDGPUConvertToISA.cpp
1 //===-- AMDGPUConvertToISA.cpp - Lower AMDIL to HW ISA --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass lowers AMDIL machine instructions to the appropriate hardware
11 // instructions.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AMDGPU.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18
19 using namespace llvm;
20
21 namespace {
22
23 class AMDGPUConvertToISAPass : public MachineFunctionPass {
24
25 private:
26 static char ID;
27 TargetMachine &TM;
28
29 public:
30 AMDGPUConvertToISAPass(TargetMachine &tm) :
31 MachineFunctionPass(ID), TM(tm) { }
32
33 virtual bool runOnMachineFunction(MachineFunction &MF);
34
35 virtual const char *getPassName() const {return "AMDGPU Convert to ISA";}
36
37 };
38
39 } // End anonymous namespace
40
41 char AMDGPUConvertToISAPass::ID = 0;
42
43 FunctionPass *llvm::createAMDGPUConvertToISAPass(TargetMachine &tm) {
44 return new AMDGPUConvertToISAPass(tm);
45 }
46
47 bool AMDGPUConvertToISAPass::runOnMachineFunction(MachineFunction &MF)
48 {
49 const AMDGPUInstrInfo * TII =
50 static_cast<const AMDGPUInstrInfo*>(TM.getInstrInfo());
51
52 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
53 BB != BB_E; ++BB) {
54 MachineBasicBlock &MBB = *BB;
55 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
56 I != MBB.end(); I = Next, Next = llvm::next(I) ) {
57 MachineInstr &MI = *I;
58 MachineInstr * newInstr = TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
59 if (!newInstr) {
60 continue;
61 }
62 MBB.insert(I, newInstr);
63 MI.eraseFromParent();
64 }
65 }
66 return false;
67 }