radeon/llvm: Remove AMDIL CMOVLOG* instruction defs
[mesa.git] / src / gallium / drivers / radeon / AMDGPUGenInstrEnums.pl
1 #===-- AMDGPUGenInstrEnums.pl - Script for generating instruction enums ----===#
2 #
3 # The LLVM Compiler Infrastructure
4 #
5 # This file is distributed under the University of Illinois Open Source
6 # License. See LICENSE.TXT for details.
7 #
8 #===-----------------------------------------------------------------------===#
9 #
10 # This perl script is used to generate the following files:
11 #
12 # 1. perl AMDGPUGenInstrEnums.pl td > AMDGPUInstrEnums.td
13 #
14 # This file contains Tablegen constants used for matching hw instructions
15 # from R600 and SI with functionally similar AMDIL instruction. It aslo
16 # contains definitions of floating point constants like pi (in hex notation)
17 # that are used in some of the shader patterns.
18 #
19 # 2. perl AMDGPUGenInstrEnums.pl h > AMDGPUInstrEnums.h
20 #
21 # This file contains cpp enums that match the constant values in
22 # AMDGPUInstrEnums.td
23 #
24 # 3. perl AMDGPUGenInstrEnums.pl inc > AMDGPUInstrEnums.include
25 #
26 # This file contains a function called GetRealAMDILOpcode which maps the
27 # constant values defined in AMDGPUInstrEnums.h to the corresponding AMDIL
28 # instructions.
29 #===-----------------------------------------------------------------------===#
30
31 use warnings;
32 use strict;
33
34 my @F32_MULTICLASSES = qw {
35 UnaryIntrinsicFloat
36 UnaryIntrinsicFloatScalar
37 TernaryIntrinsicFloat
38 BinaryOpMCFloat
39 };
40
41 my @I32_MULTICLASSES = qw {
42 BinaryOpMCInt
43 BinaryOpMCi32
44 BinaryOpMCi32Const
45 };
46
47 my @GENERATION_ENUM = qw {
48 R600_CAYMAN
49 R600
50 EG
51 EG_CAYMAN
52 CAYMAN
53 SI
54 };
55
56 my $FILE_TYPE = $ARGV[0];
57
58 open AMDIL, '<', 'AMDILInstructions.td';
59
60 my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'MIN_f32');
61
62 while (<AMDIL>) {
63 if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
64 if (grep {$_ eq $2} @F32_MULTICLASSES) {
65 push @INST_ENUMS, "$1\_f32";
66
67 } elsif (grep {$_ eq $2} @I32_MULTICLASSES) {
68 push @INST_ENUMS, "$1\_i32";
69 }
70 } elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {
71 push @INST_ENUMS, "$1$2";
72 }
73 }
74
75 if ($FILE_TYPE eq 'td') {
76
77 print_td_enum('AMDILInst', 'AMDILInstEnums', 'field bits<16>', @INST_ENUMS);
78
79 print_td_enum('AMDGPUGen', 'AMDGPUGenEnums', 'field bits<3>', @GENERATION_ENUM);
80
81 my %constants = (
82 'PI' => '0x40490fdb',
83 'TWO_PI' => '0x40c90fdb',
84 'TWO_PI_INV' => '0x3e22f983'
85 );
86
87 print "class Constants {\n";
88 foreach (keys(%constants)) {
89 print "int $_ = $constants{$_};\n";
90 }
91 print "}\n";
92 print "def CONST : Constants;\n";
93
94 } elsif ($FILE_TYPE eq 'h') {
95
96 print "unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;\n";
97
98 print_h_enum('AMDILTblgenOpcode', @INST_ENUMS);
99
100 print_h_enum('AMDGPUGen', @GENERATION_ENUM);
101
102 } elsif ($FILE_TYPE eq 'inc') {
103 print "unsigned AMDGPUInstrInfo::GetRealAMDILOpcode(unsigned internalOpcode) const\n{\n";
104 print " switch(internalOpcode) {\n";
105 #Start at 1 so we skip NONE
106 for (my $i = 1; $i < scalar(@INST_ENUMS); $i++) {
107 my $inst = $INST_ENUMS[$i];
108 print " case AMDGPUInstrInfo::$inst: return AMDIL::$inst;\n";
109 }
110 print " default: abort();\n";
111 print " }\n}\n";
112 }
113
114
115 sub print_td_enum {
116 my ($instance, $class, $field, @values) = @_;
117
118 print "class $class {\n";
119
120 for (my $i = 0; $i < scalar(@values); $i++) {
121 print " $field $values[$i] = $i;\n";
122 }
123 print "}\n";
124
125 print "def $instance : $class;\n";
126 }
127
128 sub print_h_enum {
129
130 my ($enum, @list) = @_;
131 print "enum $enum {\n";
132
133 for (my $i = 0; $i < scalar(@list); $i++) {
134 print " $list[$i] = $i";
135 if ($i != $#list) {
136 print ',';
137 }
138 print "\n";
139 }
140 print "};\n";
141 }
142