1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the parent TargetLowering class for hardware code gen targets.
12 //===----------------------------------------------------------------------===//
14 #include "AMDGPUISelLowering.h"
15 #include "AMDILIntrinsicInfo.h"
16 #include "AMDGPUUtil.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine
&TM
) :
22 AMDILTargetLowering(TM
)
24 // We need to custom lower some of the intrinsics
25 setOperationAction(ISD::INTRINSIC_WO_CHAIN
, MVT::Other
, Custom
);
28 SDValue
AMDGPUTargetLowering::LowerOperation(SDValue Op
, SelectionDAG
&DAG
)
31 switch (Op
.getOpcode()) {
32 default: return AMDILTargetLowering::LowerOperation(Op
, DAG
);
33 case ISD::INTRINSIC_WO_CHAIN
: return LowerINTRINSIC_WO_CHAIN(Op
, DAG
);
37 SDValue
AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op
,
38 SelectionDAG
&DAG
) const
40 unsigned IntrinsicID
= cast
<ConstantSDNode
>(Op
.getOperand(0))->getZExtValue();
41 DebugLoc DL
= Op
.getDebugLoc();
42 EVT VT
= Op
.getValueType();
44 switch (IntrinsicID
) {
46 case AMDGPUIntrinsic::AMDIL_abs
:
47 return LowerIntrinsicIABS(Op
, DAG
);
48 case AMDGPUIntrinsic::AMDIL_max
:
49 return DAG
.getNode(AMDGPUISD::FMAX
, DL
, VT
, Op
.getOperand(1),
51 case AMDGPUIntrinsic::AMDGPU_imax
:
52 return DAG
.getNode(AMDGPUISD::SMAX
, DL
, VT
, Op
.getOperand(1),
54 case AMDGPUIntrinsic::AMDGPU_umax
:
55 return DAG
.getNode(AMDGPUISD::UMAX
, DL
, VT
, Op
.getOperand(1),
60 ///IABS(a) = SMAX(sub(0, a), a)
61 SDValue
AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op
,
62 SelectionDAG
&DAG
) const
65 DebugLoc DL
= Op
.getDebugLoc();
66 EVT VT
= Op
.getValueType();
67 SDValue Neg
= DAG
.getNode(ISD::SUB
, DL
, VT
, DAG
.getConstant(0, VT
),
70 return DAG
.getNode(AMDGPUISD::SMAX
, DL
, VT
, Neg
, Op
.getOperand(1));
73 void AMDGPUTargetLowering::addLiveIn(MachineInstr
* MI
,
74 MachineFunction
* MF
, MachineRegisterInfo
& MRI
,
75 const TargetInstrInfo
* TII
, unsigned reg
) const
77 AMDGPU::utilAddLiveIn(MF
, MRI
, TII
, reg
, MI
->getOperand(0).getReg());
80 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
82 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode
) const
85 default: return AMDILTargetLowering::getTargetNodeName(Opcode
);