src/gallium/drivers/radeon/AMDGPUISelLowering.h

   1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the interface defintiion of the TargetLowering class
  11 // that is common to all AMD GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDGPUISELLOWERING_H
  16 #define AMDGPUISELLOWERING_H
  17
  18 #include "AMDILISelLowering.h"
  19
  20 namespace llvm {
  21
  22 class AMDGPUTargetLowering : public AMDILTargetLowering
  23 {
  24 private:
  25   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  26   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
  27
  28 protected:
  29
  30   /// addLiveIn - This functions adds reg to the live in list of the entry block
  31   /// and emits a copy from reg to MI.getOperand(0).
  32   ///
  33   //  Some registers are loaded with values before the program
  34   /// begins to execute.  The loading of these values is modeled with pseudo
  35   /// instructions which are lowered using this function.
  36   void addLiveIn(MachineInstr * MI, MachineFunction * MF,
  37                  MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
  38                  unsigned reg) const;
  39
  40   bool isHWTrueValue(SDValue Op) const;
  41   bool isHWFalseValue(SDValue Op) const;
  42
  43 public:
  44   AMDGPUTargetLowering(TargetMachine &TM);
  45
  46   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  47   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
  48   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
  49   virtual const char* getTargetNodeName(unsigned Opcode) const;
  50
  51 };
  52
  53 namespace AMDGPUISD
  54 {
  55
  56 enum
  57 {
  58   AMDGPU_FIRST = AMDILISD::LAST_ISD_NUMBER,
  59   BITALIGN,
  60   FRACT,
  61   FMAX,
  62   SMAX,
  63   UMAX,
  64   FMIN,
  65   SMIN,
  66   UMIN,
  67   URECIP,
  68   LAST_AMDGPU_ISD_NUMBER
  69 };
  70
  71
  72 } // End namespace AMDGPUISD
  73
  74 } // End namespace llvm
  75
  76 #endif // AMDGPUISELLOWERING_H