src/gallium/drivers/radeon/AMDGPUISelLowering.h

   1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the interface defintiion of the TargetLowering class
  11 // that is common to all AMD GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDGPUISELLOWERING_H
  16 #define AMDGPUISELLOWERING_H
  17
  18 #include "AMDILISelLowering.h"
  19
  20 namespace llvm {
  21
  22 class AMDGPUTargetLowering : public AMDILTargetLowering
  23 {
  24 private:
  25   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  26   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
  27   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
  28
  29 protected:
  30
  31   /// addLiveIn - This functions adds reg to the live in list of the entry block
  32   /// and emits a copy from reg to MI.getOperand(0).
  33   ///
  34   //  Some registers are loaded with values before the program
  35   /// begins to execute.  The loading of these values is modeled with pseudo
  36   /// instructions which are lowered using this function.
  37   void addLiveIn(MachineInstr * MI, MachineFunction * MF,
  38                  MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
  39                  unsigned reg) const;
  40
  41   bool isHWTrueValue(SDValue Op) const;
  42   bool isHWFalseValue(SDValue Op) const;
  43
  44 public:
  45   AMDGPUTargetLowering(TargetMachine &TM);
  46
  47   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  48   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
  49   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
  50   virtual const char* getTargetNodeName(unsigned Opcode) const;
  51
  52 };
  53
  54 namespace AMDGPUISD
  55 {
  56
  57 enum
  58 {
  59   AMDGPU_FIRST = AMDILISD::LAST_ISD_NUMBER,
  60   BITALIGN,
  61   FRACT,
  62   FMAX,
  63   SMAX,
  64   UMAX,
  65   FMIN,
  66   SMIN,
  67   UMIN,
  68   URECIP,
  69   LAST_AMDGPU_ISD_NUMBER
  70 };
  71
  72
  73 } // End namespace AMDGPUISD
  74
  75 } // End namespace llvm
  76
  77 #endif // AMDGPUISELLOWERING_H