src/gallium/drivers/radeon/AMDGPUISelLowering.h

   1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the interface defintiion of the TargetLowering class
  11 // that is common to all AMD GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDGPUISELLOWERING_H
  16 #define AMDGPUISELLOWERING_H
  17
  18 #include "AMDILISelLowering.h"
  19
  20 namespace llvm {
  21
  22 class AMDGPUTargetLowering : public AMDILTargetLowering
  23 {
  24 private:
  25   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  26
  27 protected:
  28
  29   /// addLiveIn - This functions adds reg to the live in list of the entry block
  30   /// and emits a copy from reg to MI.getOperand(0).
  31   ///
  32   //  Some registers are loaded with values before the program
  33   /// begins to execute.  The loading of these values is modeled with pseudo
  34   /// instructions which are lowered using this function.
  35   void addLiveIn(MachineInstr * MI, MachineFunction * MF,
  36                  MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
  37                  unsigned reg) const;
  38
  39 public:
  40   AMDGPUTargetLowering(TargetMachine &TM);
  41
  42   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  43   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
  44   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
  45   virtual const char* getTargetNodeName(unsigned Opcode) const;
  46
  47 };
  48
  49 namespace AMDGPUISD
  50 {
  51
  52 enum
  53 {
  54   AMDGPU_FIRST = AMDILISD::LAST_NON_MEMORY_OPCODE,
  55   FMAX,
  56   SMAX,
  57   UMAX,
  58   FMIN,
  59   SMIN,
  60   UMIN,
  61   LAST_AMDGPU_ISD_NUMBER
  62 };
  63
  64
  65 } // End namespace AMDGPUISD
  66
  67 } // End namespace llvm
  68
  69 #endif // AMDGPUISELLOWERING_H