src/gallium/drivers/radeon/AMDGPUISelLowering.h

   1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the interface defintiion of the TargetLowering class
  11 // that is common to all AMD GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDGPUISELLOWERING_H
  16 #define AMDGPUISELLOWERING_H
  17
  18 #include "llvm/Target/TargetLowering.h"
  19
  20 namespace llvm {
  21
  22 class MachineRegisterInfo;
  23
  24 class AMDGPUTargetLowering : public TargetLowering
  25 {
  26 private:
  27   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  28   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
  29
  30 protected:
  31
  32   /// addLiveIn - This functions adds reg to the live in list of the entry block
  33   /// and emits a copy from reg to MI.getOperand(0).
  34   ///
  35   //  Some registers are loaded with values before the program
  36   /// begins to execute.  The loading of these values is modeled with pseudo
  37   /// instructions which are lowered using this function.
  38   void addLiveIn(MachineInstr * MI, MachineFunction * MF,
  39                  MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
  40                  unsigned reg) const;
  41
  42   bool isHWTrueValue(SDValue Op) const;
  43   bool isHWFalseValue(SDValue Op) const;
  44
  45 public:
  46   AMDGPUTargetLowering(TargetMachine &TM);
  47
  48   virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
  49                              bool isVarArg,
  50                              const SmallVectorImpl<ISD::InputArg> &Ins,
  51                              DebugLoc DL, SelectionDAG &DAG,
  52                              SmallVectorImpl<SDValue> &InVals) const;
  53
  54   virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
  55                               bool isVarArg,
  56                               const SmallVectorImpl<ISD::OutputArg> &Outs,
  57                               const SmallVectorImpl<SDValue> &OutVals,
  58                               DebugLoc DL, SelectionDAG &DAG) const;
  59
  60   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  61   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
  62   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
  63   virtual const char* getTargetNodeName(unsigned Opcode) const;
  64
  65 // Functions defined in AMDILISelLowering.cpp
  66 public:
  67
  68   /// computeMaskedBitsForTargetNode - Determine which of the bits specified
  69   /// in Mask are known to be either zero or one and return them in the
  70   /// KnownZero/KnownOne bitsets.
  71   virtual void computeMaskedBitsForTargetNode(const SDValue Op,
  72                                               APInt &KnownZero,
  73                                               APInt &KnownOne,
  74                                               const SelectionDAG &DAG,
  75                                               unsigned Depth = 0) const;
  76
  77   virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
  78                                   const CallInst &I, unsigned Intrinsic) const;
  79
  80   /// isFPImmLegal - We want to mark f32/f64 floating point values as legal.
  81   bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
  82
  83   /// ShouldShrinkFPConstant - We don't want to shrink f64/f32 constants.
  84   bool ShouldShrinkFPConstant(EVT VT) const;
  85
  86 private:
  87   void InitAMDILLowering();
  88   SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
  89   SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
  90   SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
  91   SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
  92   SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
  93   SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
  94   SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
  95   SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
  96   SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
  97   SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
  98   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
  99   EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
 100   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 101   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 102 };
 103
 104 namespace AMDGPUISD
 105 {
 106
 107 enum
 108 {
 109   // AMDIL ISD Opcodes
 110   FIRST_NUMBER = ISD::BUILTIN_OP_END,
 111   MAD,         // 32bit Fused Multiply Add instruction
 112   VBUILD,      // scalar to vector mov instruction
 113   CALL,        // Function call based on a single integer
 114   UMUL,        // 32bit unsigned multiplication
 115   DIV_INF,      // Divide with infinity returned on zero divisor
 116   RET_FLAG,
 117   BRANCH_COND,
 118   // End AMDIL ISD Opcodes
 119   BITALIGN,
 120   FRACT,
 121   FMAX,
 122   SMAX,
 123   UMAX,
 124   FMIN,
 125   SMIN,
 126   UMIN,
 127   URECIP,
 128   LAST_AMDGPU_ISD_NUMBER
 129 };
 130
 131
 132 } // End namespace AMDGPUISD
 133
 134 namespace SIISD {
 135
 136 enum {
 137   SI_FIRST = AMDGPUISD::LAST_AMDGPU_ISD_NUMBER,
 138   VCC_AND,
 139   VCC_BITCAST
 140 };
 141
 142 } // End namespace SIISD
 143
 144 } // End namespace llvm
 145
 146 #endif // AMDGPUISELLOWERING_H