1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the TargetInstrInfo class that is
11 // common to all AMD GPUs.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUInstrInfo.h"
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 AMDGPUInstrInfo::AMDGPUInstrInfo(AMDGPUTargetMachine
&tm
)
24 : AMDILInstrInfo(tm
), TM(tm
) { }
26 MachineInstr
* AMDGPUInstrInfo::convertToISA(MachineInstr
& MI
, MachineFunction
&MF
,
29 MachineInstrBuilder newInstr
;
30 MachineRegisterInfo
&MRI
= MF
.getRegInfo();
31 const AMDGPURegisterInfo
& RI
= getRegisterInfo();
33 // Create the new instruction
34 newInstr
= BuildMI(MF
, DL
, TM
.getInstrInfo()->get(MI
.getOpcode()));
36 for (unsigned i
= 0; i
< MI
.getNumOperands(); i
++) {
37 MachineOperand
&MO
= MI
.getOperand(i
);
38 // Convert dst regclass to one that is supported by the ISA
39 if (MO
.isReg() && MO
.isDef()) {
40 if (TargetRegisterInfo::isVirtualRegister(MO
.getReg())) {
41 const TargetRegisterClass
* oldRegClass
= MRI
.getRegClass(MO
.getReg());
42 const TargetRegisterClass
* newRegClass
= RI
.getISARegClass(oldRegClass
);
46 MRI
.setRegClass(MO
.getReg(), newRegClass
);
49 // Add the operand to the new instruction
50 newInstr
.addOperand(MO
);