radeon/llvm: Move lowering of SETCC node to R600ISelLowering
[mesa.git] / src / gallium / drivers / radeon / AMDGPUInstrInfo.cpp
1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the implementation of the TargetInstrInfo class that is
11 // common to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AMDGPUInstrInfo.h"
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "AMDIL.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20
21 using namespace llvm;
22
23 AMDGPUInstrInfo::AMDGPUInstrInfo(AMDGPUTargetMachine &tm)
24 : AMDILInstrInfo(tm), TM(tm) { }
25
26 MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
27 DebugLoc DL) const
28 {
29 MachineInstrBuilder newInstr;
30 MachineRegisterInfo &MRI = MF.getRegInfo();
31 const AMDGPURegisterInfo & RI = getRegisterInfo();
32
33 // Create the new instruction
34 newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(MI.getOpcode()));
35
36 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
37 MachineOperand &MO = MI.getOperand(i);
38 // Convert dst regclass to one that is supported by the ISA
39 if (MO.isReg() && MO.isDef()) {
40 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
41 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
42 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
43
44 assert(newRegClass);
45
46 MRI.setRegClass(MO.getReg(), newRegClass);
47 }
48 }
49 // Add the operand to the new instruction
50 newInstr.addOperand(MO);
51 }
52
53 return newInstr;
54 }