src/gallium/drivers/radeon/AMDGPUInstructions.td

   1 //===-- AMDGPUInstructions.td - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "AMDGPUInstrEnums.td"
  15
  16 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
  17   field bits<16> AMDILOp = 0;
  18   field bits<3> Gen = 0;
  19   field bit PreloadReg = 0;
  20
  21   let Namespace = "AMDIL";
  22   let OutOperandList = outs;
  23   let InOperandList = ins;
  24   let AsmString = asm;
  25   let Pattern = pattern;
  26   let TSFlags{32} = PreloadReg;
  27   let TSFlags{42-40} = Gen;
  28   let TSFlags{63-48} = AMDILOp;
  29 }
  30
  31 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
  32     : AMDGPUInst<outs, ins, asm, pattern> {
  33
  34   field bits<32> Inst = 0xffffffff;
  35
  36 }
  37
  38 let isCodeGenOnly = 1 in {
  39
  40   def EXPORT_REG : AMDGPUShaderInst <
  41     (outs),
  42     (ins GPRF32:$src),
  43     "EXPORT_REG $src",
  44     [(int_AMDGPU_export_reg GPRF32:$src)]
  45   >;
  46
  47   def LOAD_INPUT : AMDGPUShaderInst <
  48     (outs GPRF32:$dst),
  49     (ins i32imm:$src),
  50     "LOAD_INPUT $dst, $src",
  51     [] >{
  52     let PreloadReg = 1;
  53   }
  54
  55   def MASK_WRITE : AMDGPUShaderInst <
  56     (outs),
  57     (ins GPRF32:$src),
  58     "MASK_WRITE $src",
  59     []
  60   >;
  61
  62   def RESERVE_REG : AMDGPUShaderInst <
  63     (outs GPRF32:$dst),
  64     (ins i32imm:$src),
  65     "RESERVE_REG $dst, $src",
  66     [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]> {
  67     let PreloadReg = 1;
  68   }
  69
  70   def STORE_OUTPUT: AMDGPUShaderInst <
  71     (outs GPRF32:$dst),
  72     (ins GPRF32:$src0, i32imm:$src1),
  73     "STORE_OUTPUT $dst, $src0, $src1",
  74     [(set GPRF32:$dst, (int_AMDGPU_store_output GPRF32:$src0, imm:$src1))]
  75   >;
  76 }
  77
  78 /* Generic helper patterns for intrinsics */
  79 /* -------------------------------------- */
  80
  81 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
  82                   RegisterClass rc> : Pat <
  83   (int_AMDGPU_pow rc:$src0, rc:$src1),
  84   (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
  85 >;
  86
  87 /* Other helper patterns */
  88 /* --------------------- */
  89
  90 /* Extract element pattern */
  91 class Extract_Element <ValueType sub_type, ValueType vec_type,
  92                      RegisterClass vec_class, int sub_idx,
  93                      SubRegIndex sub_reg>: Pat<
  94   (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
  95   (EXTRACT_SUBREG vec_class:$src, sub_reg)
  96 >;
  97
  98 /* Insert element pattern */
  99 class Insert_Element <ValueType elem_type, ValueType vec_type,
 100                       RegisterClass elem_class, RegisterClass vec_class,
 101                       int sub_idx, SubRegIndex sub_reg> : Pat <
 102
 103   (vec_type (vector_insert (vec_type vec_class:$vec),
 104                            (elem_type elem_class:$elem), sub_idx)),
 105   (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
 106 >;
 107
 108 include "R600Instructions.td"
 109
 110 include "SIInstrInfo.td"
 111