src/gallium/drivers/radeon/AMDGPUInstructions.td

   1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains instruction defs that are common to all hw codegen
  11 // targets.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
  16   field bits<16> AMDILOp = 0;
  17   field bits<3> Gen = 0;
  18
  19   let Namespace = "AMDGPU";
  20   let OutOperandList = outs;
  21   let InOperandList = ins;
  22   let AsmString = asm;
  23   let Pattern = pattern;
  24   let Itinerary = NullALU;
  25   let TSFlags{42-40} = Gen;
  26   let TSFlags{63-48} = AMDILOp;
  27 }
  28
  29 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
  30     : AMDGPUInst<outs, ins, asm, pattern> {
  31
  32   field bits<32> Inst = 0xffffffff;
  33
  34 }
  35
  36 def COND_EQ : PatLeaf <
  37   (cond),
  38   [{switch(N->get()){{default: return false;
  39                      case ISD::SETOEQ: case ISD::SETUEQ:
  40                      case ISD::SETEQ: return true;}}}]
  41 >;
  42
  43 def COND_NE : PatLeaf <
  44   (cond),
  45   [{switch(N->get()){{default: return false;
  46                      case ISD::SETONE: case ISD::SETUNE:
  47                      case ISD::SETNE: return true;}}}]
  48 >;
  49 def COND_GT : PatLeaf <
  50   (cond),
  51   [{switch(N->get()){{default: return false;
  52                      case ISD::SETOGT: case ISD::SETUGT:
  53                      case ISD::SETGT: return true;}}}]
  54 >;
  55
  56 def COND_GE : PatLeaf <
  57   (cond),
  58   [{switch(N->get()){{default: return false;
  59                      case ISD::SETOGE: case ISD::SETUGE:
  60                      case ISD::SETGE: return true;}}}]
  61 >;
  62
  63 def COND_LT : PatLeaf <
  64   (cond),
  65   [{switch(N->get()){{default: return false;
  66                      case ISD::SETOLT: case ISD::SETULT:
  67                      case ISD::SETLT: return true;}}}]
  68 >;
  69
  70 def COND_LE : PatLeaf <
  71   (cond),
  72   [{switch(N->get()){{default: return false;
  73                      case ISD::SETOLE: case ISD::SETULE:
  74                      case ISD::SETLE: return true;}}}]
  75 >;
  76
  77 //===----------------------------------------------------------------------===//
  78 // Load/Store Pattern Fragments
  79 //===----------------------------------------------------------------------===//
  80
  81 def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
  82     return isGlobalLoad(dyn_cast<LoadSDNode>(N));
  83 }]>;
  84
  85 class Constants {
  86 int TWO_PI = 0x40c90fdb;
  87 int PI = 0x40490fdb;
  88 int TWO_PI_INV = 0x3e22f983;
  89 }
  90 def CONST : Constants;
  91
  92 def FP_ZERO : PatLeaf <
  93   (fpimm),
  94   [{return N->getValueAPF().isZero();}]
  95 >;
  96
  97 def FP_ONE : PatLeaf <
  98   (fpimm),
  99   [{return N->isExactlyValue(1.0);}]
 100 >;
 101
 102 let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1  in {
 103
 104 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
 105   (outs rc:$dst),
 106   (ins rc:$src0),
 107   "CLAMP $dst, $src0",
 108   [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
 109 >;
 110
 111 class FABS <RegisterClass rc> : AMDGPUShaderInst <
 112   (outs rc:$dst),
 113   (ins rc:$src0),
 114   "FABS $dst, $src0",
 115   [(set rc:$dst, (fabs rc:$src0))]
 116 >;
 117
 118 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
 119   (outs rc:$dst),
 120   (ins rc:$src0),
 121   "FNEG $dst, $src0",
 122   [(set rc:$dst, (fneg rc:$src0))]
 123 >;
 124
 125 def SHADER_TYPE : AMDGPUShaderInst <
 126   (outs),
 127   (ins i32imm:$type),
 128   "SHADER_TYPE $type",
 129   [(int_AMDGPU_shader_type imm:$type)]
 130 >;
 131
 132 } // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1
 133
 134 /* Generic helper patterns for intrinsics */
 135 /* -------------------------------------- */
 136
 137 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
 138                   RegisterClass rc> : Pat <
 139   (fpow rc:$src0, rc:$src1),
 140   (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
 141 >;
 142
 143 /* Other helper patterns */
 144 /* --------------------- */
 145
 146 /* Extract element pattern */
 147 class Extract_Element <ValueType sub_type, ValueType vec_type,
 148                      RegisterClass vec_class, int sub_idx,
 149                      SubRegIndex sub_reg>: Pat<
 150   (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
 151   (EXTRACT_SUBREG vec_class:$src, sub_reg)
 152 >;
 153
 154 /* Insert element pattern */
 155 class Insert_Element <ValueType elem_type, ValueType vec_type,
 156                       RegisterClass elem_class, RegisterClass vec_class,
 157                       int sub_idx, SubRegIndex sub_reg> : Pat <
 158
 159   (vec_type (vector_insert (vec_type vec_class:$vec),
 160                            (elem_type elem_class:$elem), sub_idx)),
 161   (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
 162 >;
 163
 164 // Vector Build pattern
 165 class Vector_Build <ValueType vecType, RegisterClass vectorClass,
 166                     ValueType elemType, RegisterClass elemClass> : Pat <
 167   (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
 168                          (elemType elemClass:$z), (elemType elemClass:$w))),
 169   (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
 170   (vecType (IMPLICIT_DEF)), elemClass:$x, sel_x), elemClass:$y, sel_y),
 171                             elemClass:$z, sel_z), elemClass:$w, sel_w)
 172 >;
 173
 174 // bitconvert pattern
 175 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
 176   (dt (bitconvert (st rc:$src0))),
 177   (dt rc:$src0)
 178 >;
 179
 180 include "R600Instructions.td"
 181
 182 include "SIInstrInfo.td"
 183