src/gallium/drivers/radeon/AMDGPUInstructions.td

   1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains instruction defs that are common to all hw codegen
  11 // targets.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
  16   field bits<16> AMDILOp = 0;
  17   field bits<3> Gen = 0;
  18
  19   let Namespace = "AMDIL";
  20   let OutOperandList = outs;
  21   let InOperandList = ins;
  22   let AsmString = asm;
  23   let Pattern = pattern;
  24   let TSFlags{42-40} = Gen;
  25   let TSFlags{63-48} = AMDILOp;
  26 }
  27
  28 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
  29     : AMDGPUInst<outs, ins, asm, pattern> {
  30
  31   field bits<32> Inst = 0xffffffff;
  32
  33 }
  34
  35 class Constants {
  36 int TWO_PI = 0x40c90fdb;
  37 int PI = 0x40490fdb;
  38 int TWO_PI_INV = 0x3e22f983;
  39 }
  40 def CONST : Constants;
  41
  42 let isCodeGenOnly = 1 in {
  43
  44   def MASK_WRITE : AMDGPUShaderInst <
  45     (outs),
  46     (ins GPRF32:$src),
  47     "MASK_WRITE $src",
  48     []
  49   >;
  50
  51 let isPseudo = 1, usesCustomInserter = 1  in {
  52
  53 class FABS <RegisterClass rc> : AMDGPUShaderInst <
  54   (outs rc:$dst),
  55   (ins rc:$src0),
  56   "FABS $dst, $src0",
  57   [(set rc:$dst, (fabs rc:$src0))]
  58 >;
  59
  60 } // End isPseudo = 1, hasCustomInserter = 1
  61
  62 } // End isCodeGenOnly = 1
  63
  64 /* Generic helper patterns for intrinsics */
  65 /* -------------------------------------- */
  66
  67 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
  68                   RegisterClass rc> : Pat <
  69   (int_AMDGPU_pow rc:$src0, rc:$src1),
  70   (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
  71 >;
  72
  73 /* Other helper patterns */
  74 /* --------------------- */
  75
  76 /* Extract element pattern */
  77 class Extract_Element <ValueType sub_type, ValueType vec_type,
  78                      RegisterClass vec_class, int sub_idx,
  79                      SubRegIndex sub_reg>: Pat<
  80   (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
  81   (EXTRACT_SUBREG vec_class:$src, sub_reg)
  82 >;
  83
  84 /* Insert element pattern */
  85 class Insert_Element <ValueType elem_type, ValueType vec_type,
  86                       RegisterClass elem_class, RegisterClass vec_class,
  87                       int sub_idx, SubRegIndex sub_reg> : Pat <
  88
  89   (vec_type (vector_insert (vec_type vec_class:$vec),
  90                            (elem_type elem_class:$elem), sub_idx)),
  91   (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
  92 >;
  93
  94 include "R600Instructions.td"
  95
  96 include "SIInstrInfo.td"
  97