src/gallium/drivers/radeon/AMDGPUInstructions.td

   1 //===-- AMDGPUInstructions.td - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "AMDGPUInstrEnums.td"
  15
  16 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
  17   field bits<16> AMDILOp = 0;
  18   field bits<3> Gen = 0;
  19
  20   let Namespace = "AMDIL";
  21   let OutOperandList = outs;
  22   let InOperandList = ins;
  23   let AsmString = asm;
  24   let Pattern = pattern;
  25   let TSFlags{42-40} = Gen;
  26   let TSFlags{63-48} = AMDILOp;
  27 }
  28
  29 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
  30     : AMDGPUInst<outs, ins, asm, pattern> {
  31
  32   field bits<32> Inst = 0xffffffff;
  33
  34 }
  35
  36 let isCodeGenOnly = 1 in {
  37
  38   def EXPORT_REG : AMDGPUShaderInst <
  39     (outs),
  40     (ins GPRF32:$src),
  41     "EXPORT_REG $src",
  42     [(int_AMDGPU_export_reg GPRF32:$src)]
  43   >;
  44
  45   def MASK_WRITE : AMDGPUShaderInst <
  46     (outs),
  47     (ins GPRF32:$src),
  48     "MASK_WRITE $src",
  49     []
  50   >;
  51
  52   def RESERVE_REG : AMDGPUShaderInst <
  53     (outs GPRF32:$dst),
  54     (ins i32imm:$src),
  55     "RESERVE_REG $dst, $src",
  56     [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]
  57   >;
  58 }
  59
  60 /* Generic helper patterns for intrinsics */
  61 /* -------------------------------------- */
  62
  63 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
  64                   RegisterClass rc> : Pat <
  65   (int_AMDGPU_pow rc:$src0, rc:$src1),
  66   (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
  67 >;
  68
  69 /* Other helper patterns */
  70 /* --------------------- */
  71
  72 /* Extract element pattern */
  73 class Extract_Element <ValueType sub_type, ValueType vec_type,
  74                      RegisterClass vec_class, int sub_idx,
  75                      SubRegIndex sub_reg>: Pat<
  76   (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
  77   (EXTRACT_SUBREG vec_class:$src, sub_reg)
  78 >;
  79
  80 /* Insert element pattern */
  81 class Insert_Element <ValueType elem_type, ValueType vec_type,
  82                       RegisterClass elem_class, RegisterClass vec_class,
  83                       int sub_idx, SubRegIndex sub_reg> : Pat <
  84
  85   (vec_type (vector_insert (vec_type vec_class:$vec),
  86                            (elem_type elem_class:$elem), sub_idx)),
  87   (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
  88 >;
  89
  90 include "R600Instructions.td"
  91
  92 include "SIInstrInfo.td"
  93