src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp

   1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Parent TargetRegisterInfo class common to all hw codegen targets.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPURegisterInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16
  17 using namespace llvm;
  18
  19 AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
  20     const TargetInstrInfo &tii)
  21 : AMDGPUGenRegisterInfo(0),
  22   TM(tm),
  23   TII(tii)
  24   { }
  25
  26 //===----------------------------------------------------------------------===//
  27 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
  28 // they are not supported at this time.
  29 //===----------------------------------------------------------------------===//
  30
  31 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
  32
  33 const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  34                                                                          const {
  35   return &CalleeSavedReg;
  36 }
  37
  38 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
  39                                              int SPAdj,
  40                                              RegScavenger *RS) const {
  41   assert(!"Subroutines not supported yet");
  42 }
  43
  44 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
  45   assert(!"Subroutines not supported yet");
  46   return 0;
  47 }
  48
  49 #define GET_REGINFO_TARGET_DESC
  50 #include "AMDGPUGenRegisterInfo.inc"