src/gallium/drivers/radeon/AMDGPURegisterInfo.h

   1 //===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the TargetRegisterInfo interface that is implemented
  11 // by all hw codegen targets.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDGPUREGISTERINFO_H_
  16 #define AMDGPUREGISTERINFO_H_
  17
  18 #include "llvm/ADT/BitVector.h"
  19 #include "llvm/Target/TargetRegisterInfo.h"
  20
  21 #define GET_REGINFO_HEADER
  22 #define GET_REGINFO_ENUM
  23 #include "AMDGPUGenRegisterInfo.inc"
  24
  25 namespace llvm {
  26
  27 class AMDGPUTargetMachine;
  28 class TargetInstrInfo;
  29
  30 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo
  31 {
  32   TargetMachine &TM;
  33   const TargetInstrInfo &TII;
  34   static const uint16_t CalleeSavedReg;
  35
  36   AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
  37
  38   virtual BitVector getReservedRegs(const MachineFunction &MF) const {
  39     assert(!"Unimplemented");  return BitVector();
  40   }
  41
  42   /// getISARegClass - rc is an AMDIL reg class.  This function returns the
  43   /// ISA reg class that is equivalent to the given AMDIL reg class.
  44   virtual const TargetRegisterClass * getISARegClass(
  45                                          const TargetRegisterClass * rc) const {
  46     assert(!"Unimplemented"); return NULL;
  47   }
  48
  49   virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
  50     assert(!"Unimplemented"); return NULL;
  51   }
  52
  53   const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
  54   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
  55                            RegScavenger *RS) const;
  56   unsigned getFrameRegister(const MachineFunction &MF) const;
  57
  58 };
  59
  60 } // End namespace llvm
  61
  62 #endif // AMDIDSAREGISTERINFO_H_