radeon/llvm: Move lowering of SETCC node to R600ISelLowering
[mesa.git] / src / gallium / drivers / radeon / AMDGPURegisterInfo.h
1 //===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the TargetRegisterInfo interface that is implemented
11 // by all hw codegen targets.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef AMDGPUREGISTERINFO_H_
16 #define AMDGPUREGISTERINFO_H_
17
18 #include "AMDILRegisterInfo.h"
19
20 namespace llvm {
21
22 class AMDGPUTargetMachine;
23 class TargetInstrInfo;
24
25 struct AMDGPURegisterInfo : public AMDILRegisterInfo
26 {
27 AMDGPUTargetMachine &TM;
28 const TargetInstrInfo &TII;
29
30 AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
31
32 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
33
34 /// getISARegClass - rc is an AMDIL reg class. This function returns the
35 /// ISA reg class that is equivalent to the given AMDIL reg class.
36 virtual const TargetRegisterClass *
37 getISARegClass(const TargetRegisterClass * rc) const = 0;
38 };
39
40 } // End namespace llvm
41
42 #endif // AMDIDSAREGISTERINFO_H_