src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp

   1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // The AMDGPU target machine contains all of the hardware specific information
  11 // needed to emit code for R600 and SI GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AMDGPUTargetMachine.h"
  16 #include "AMDGPU.h"
  17 #include "R600ISelLowering.h"
  18 #include "R600InstrInfo.h"
  19 #include "SIISelLowering.h"
  20 #include "SIInstrInfo.h"
  21 #include "llvm/Analysis/Passes.h"
  22 #include "llvm/Analysis/Verifier.h"
  23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
  24 #include "llvm/CodeGen/MachineModuleInfo.h"
  25 #include "llvm/CodeGen/Passes.h"
  26 #include "llvm/MC/MCAsmInfo.h"
  27 #include "llvm/PassManager.h"
  28 #include "llvm/Support/TargetRegistry.h"
  29 #include "llvm/Support/raw_os_ostream.h"
  30 #include "llvm/Transforms/IPO.h"
  31 #include "llvm/Transforms/Scalar.h"
  32
  33 using namespace llvm;
  34
  35 extern "C" void LLVMInitializeAMDGPUTarget() {
  36   // Register the target
  37   RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
  38 }
  39
  40 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
  41     StringRef CPU, StringRef FS,
  42   TargetOptions Options,
  43   Reloc::Model RM, CodeModel::Model CM,
  44   CodeGenOpt::Level OptLevel
  45 )
  46 :
  47   LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
  48   Subtarget(TT, CPU, FS),
  49   DataLayout(Subtarget.getDataLayout()),
  50   FrameLowering(TargetFrameLowering::StackGrowsUp,
  51       Subtarget.device()->getStackAlignment(), 0),
  52   IntrinsicInfo(this),
  53   InstrItins(&Subtarget.getInstrItineraryData()),
  54   mDump(false)
  55
  56 {
  57   // TLInfo uses InstrInfo so it must be initialized after.
  58   if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
  59     InstrInfo = new R600InstrInfo(*this);
  60     TLInfo = new R600TargetLowering(*this);
  61   } else {
  62     InstrInfo = new SIInstrInfo(*this);
  63     TLInfo = new SITargetLowering(*this);
  64   }
  65 }
  66
  67 AMDGPUTargetMachine::~AMDGPUTargetMachine()
  68 {
  69 }
  70
  71 bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  72                                               formatted_raw_ostream &Out,
  73                                               CodeGenFileType FileType,
  74                                               bool DisableVerify) {
  75   // XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
  76   // only using it to access addPassesToGenerateCode()
  77   bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
  78                                                      DisableVerify);
  79   assert(fail);
  80
  81   const AMDILSubtarget &STM = getSubtarget<AMDILSubtarget>();
  82   std::string gpu = STM.getDeviceName();
  83   if (gpu == "SI") {
  84     PM.add(createSICodeEmitterPass(Out));
  85   } else if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
  86     PM.add(createR600CodeEmitterPass(Out));
  87   } else {
  88     abort();
  89     return true;
  90   }
  91   PM.add(createGCInfoDeleter());
  92
  93   return false;
  94 }
  95
  96 namespace {
  97 class AMDGPUPassConfig : public TargetPassConfig {
  98 public:
  99   AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
 100     : TargetPassConfig(TM, PM) {}
 101
 102   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
 103     return getTM<AMDGPUTargetMachine>();
 104   }
 105
 106   virtual bool addPreISel();
 107   virtual bool addInstSelector();
 108   virtual bool addPreRegAlloc();
 109   virtual bool addPostRegAlloc();
 110   virtual bool addPreSched2();
 111   virtual bool addPreEmitPass();
 112 };
 113 } // End of anonymous namespace
 114
 115 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
 116   return new AMDGPUPassConfig(this, PM);
 117 }
 118
 119 bool
 120 AMDGPUPassConfig::addPreISel()
 121 {
 122   const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
 123   if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
 124     PM->add(createR600KernelParametersPass(
 125                      getAMDGPUTargetMachine().getTargetData()));
 126   }
 127   return false;
 128 }
 129
 130 bool AMDGPUPassConfig::addInstSelector() {
 131   PM->add(createAMDILPeepholeOpt(*TM));
 132   PM->add(createAMDILISelDag(getAMDGPUTargetMachine()));
 133   return false;
 134 }
 135
 136 bool AMDGPUPassConfig::addPreRegAlloc() {
 137   const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
 138
 139   if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
 140     PM->add(createSIAssignInterpRegsPass(*TM));
 141   }
 142   PM->add(createAMDGPUConvertToISAPass(*TM));
 143   return false;
 144 }
 145
 146 bool AMDGPUPassConfig::addPostRegAlloc() {
 147   return false;
 148 }
 149
 150 bool AMDGPUPassConfig::addPreSched2() {
 151   return false;
 152 }
 153
 154 bool AMDGPUPassConfig::addPreEmitPass() {
 155   PM->add(createAMDILCFGPreparationPass(*TM));
 156   PM->add(createAMDILCFGStructurizerPass(*TM));
 157
 158   return false;
 159 }
 160