src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp

   1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // The AMDGPU target machine contains all of the hardware specific information
  11 // needed to emit code for R600 and SI GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AMDGPUTargetMachine.h"
  16 #include "AMDGPU.h"
  17 #include "R600ISelLowering.h"
  18 #include "R600InstrInfo.h"
  19 #include "SIISelLowering.h"
  20 #include "SIInstrInfo.h"
  21 #include "llvm/Analysis/Passes.h"
  22 #include "llvm/Analysis/Verifier.h"
  23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
  24 #include "llvm/CodeGen/MachineModuleInfo.h"
  25 #include "llvm/CodeGen/Passes.h"
  26 #include "llvm/MC/MCAsmInfo.h"
  27 #include "llvm/PassManager.h"
  28 #include "llvm/Support/TargetRegistry.h"
  29 #include "llvm/Support/raw_os_ostream.h"
  30 #include "llvm/Transforms/IPO.h"
  31 #include "llvm/Transforms/Scalar.h"
  32 #include <llvm/CodeGen/Passes.h>
  33
  34 using namespace llvm;
  35
  36 extern "C" void LLVMInitializeAMDGPUTarget() {
  37   // Register the target
  38   RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
  39 }
  40
  41 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
  42     StringRef CPU, StringRef FS,
  43   TargetOptions Options,
  44   Reloc::Model RM, CodeModel::Model CM,
  45   CodeGenOpt::Level OptLevel
  46 )
  47 :
  48   LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
  49   Subtarget(TT, CPU, FS),
  50   DataLayout(Subtarget.getDataLayout()),
  51   FrameLowering(TargetFrameLowering::StackGrowsUp,
  52       Subtarget.device()->getStackAlignment(), 0),
  53   IntrinsicInfo(this),
  54   InstrItins(&Subtarget.getInstrItineraryData()),
  55   mDump(false)
  56
  57 {
  58   // TLInfo uses InstrInfo so it must be initialized after.
  59   if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
  60     InstrInfo = new R600InstrInfo(*this);
  61     TLInfo = new R600TargetLowering(*this);
  62   } else {
  63     InstrInfo = new SIInstrInfo(*this);
  64     TLInfo = new SITargetLowering(*this);
  65   }
  66 }
  67
  68 AMDGPUTargetMachine::~AMDGPUTargetMachine()
  69 {
  70 }
  71
  72 bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  73                                               formatted_raw_ostream &Out,
  74                                               CodeGenFileType FileType,
  75                                               bool DisableVerify) {
  76   // XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
  77   // only using it to access addPassesToGenerateCode()
  78   bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
  79                                                      DisableVerify);
  80   assert(fail);
  81
  82   const AMDGPUSubtarget &STM = getSubtarget<AMDGPUSubtarget>();
  83   std::string gpu = STM.getDeviceName();
  84   if (gpu == "SI") {
  85     PM.add(createSICodeEmitterPass(Out));
  86   } else if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
  87     PM.add(createR600CodeEmitterPass(Out));
  88   } else {
  89     abort();
  90     return true;
  91   }
  92   PM.add(createGCInfoDeleter());
  93
  94   return false;
  95 }
  96
  97 namespace {
  98 class AMDGPUPassConfig : public TargetPassConfig {
  99 public:
 100   AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
 101     : TargetPassConfig(TM, PM) {}
 102
 103   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
 104     return getTM<AMDGPUTargetMachine>();
 105   }
 106
 107   virtual bool addPreISel();
 108   virtual bool addInstSelector();
 109   virtual bool addPreRegAlloc();
 110   virtual bool addPostRegAlloc();
 111   virtual bool addPreSched2();
 112   virtual bool addPreEmitPass();
 113 };
 114 } // End of anonymous namespace
 115
 116 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
 117   return new AMDGPUPassConfig(this, PM);
 118 }
 119
 120 bool
 121 AMDGPUPassConfig::addPreISel()
 122 {
 123   const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
 124   if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
 125     PM->add(createR600KernelParametersPass(
 126                      getAMDGPUTargetMachine().getTargetData()));
 127   }
 128   return false;
 129 }
 130
 131 bool AMDGPUPassConfig::addInstSelector() {
 132   PM->add(createAMDGPUPeepholeOpt(*TM));
 133   PM->add(createAMDGPUISelDag(getAMDGPUTargetMachine()));
 134   return false;
 135 }
 136
 137 bool AMDGPUPassConfig::addPreRegAlloc() {
 138   const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
 139
 140   if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
 141     PM->add(createSIAssignInterpRegsPass(*TM));
 142   }
 143   PM->add(createAMDGPUConvertToISAPass(*TM));
 144   return false;
 145 }
 146
 147 bool AMDGPUPassConfig::addPostRegAlloc() {
 148   return false;
 149 }
 150
 151 bool AMDGPUPassConfig::addPreSched2() {
 152
 153   addPass(IfConverterID);
 154   return false;
 155 }
 156
 157 bool AMDGPUPassConfig::addPreEmitPass() {
 158   PM->add(createAMDGPUCFGPreparationPass(*TM));
 159   PM->add(createAMDGPUCFGStructurizerPass(*TM));
 160
 161   return false;
 162 }
 163