src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp

   1 //===-- AMDGPUTargetMachine.cpp - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPUTargetMachine.h"
  15 #include "AMDGPU.h"
  16 #include "AMDILTargetMachine.h"
  17 #include "R600ISelLowering.h"
  18 #include "R600InstrInfo.h"
  19 #include "R600KernelParameters.h"
  20 #include "SIISelLowering.h"
  21 #include "SIInstrInfo.h"
  22 #include "llvm/Analysis/Passes.h"
  23 #include "llvm/Analysis/Verifier.h"
  24 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
  25 #include "llvm/CodeGen/MachineModuleInfo.h"
  26 #include "llvm/CodeGen/Passes.h"
  27 #include "llvm/MC/MCAsmInfo.h"
  28 #include "llvm/PassManager.h"
  29 #include "llvm/Support/TargetRegistry.h"
  30 #include "llvm/Support/raw_os_ostream.h"
  31 #include "llvm/Transforms/IPO.h"
  32 #include "llvm/Transforms/Scalar.h"
  33
  34 using namespace llvm;
  35
  36 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
  37     StringRef CPU, StringRef FS,
  38   TargetOptions Options,
  39   Reloc::Model RM, CodeModel::Model CM,
  40   CodeGenOpt::Level OptLevel
  41 )
  42 :
  43   AMDILTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
  44   Subtarget(TT, CPU, FS),
  45   mDump(false)
  46
  47 {
  48   /* TLInfo uses InstrInfo so it must be initialized after. */
  49   if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
  50     InstrInfo = new R600InstrInfo(*this);
  51     TLInfo = new R600TargetLowering(*this);
  52   } else {
  53     InstrInfo = new SIInstrInfo(*this);
  54     TLInfo = new SITargetLowering(*this);
  55   }
  56 }
  57
  58 AMDGPUTargetMachine::~AMDGPUTargetMachine()
  59 {
  60 }
  61
  62 bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  63                                               formatted_raw_ostream &Out,
  64                                               CodeGenFileType FileType,
  65                                               bool DisableVerify) {
  66   /* XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
  67    * only using it to access addPassesToGenerateCode() */
  68   bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
  69                                                      DisableVerify);
  70   assert(fail);
  71
  72   const AMDILSubtarget &STM = getSubtarget<AMDILSubtarget>();
  73   std::string gpu = STM.getDeviceName();
  74   if (gpu == "SI") {
  75     PM.add(createSICodeEmitterPass(Out));
  76   } else if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
  77     PM.add(createR600CodeEmitterPass(Out));
  78   } else {
  79     abort();
  80     return true;
  81   }
  82   PM.add(createGCInfoDeleter());
  83
  84   return false;
  85 }
  86
  87 namespace {
  88 class AMDGPUPassConfig : public TargetPassConfig {
  89 public:
  90   AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
  91     : TargetPassConfig(TM, PM) {}
  92
  93   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
  94     return getTM<AMDGPUTargetMachine>();
  95   }
  96
  97   virtual bool addPreISel();
  98   virtual bool addInstSelector();
  99   virtual bool addPreRegAlloc();
 100   virtual bool addPostRegAlloc();
 101   virtual bool addPreSched2();
 102   virtual bool addPreEmitPass();
 103 };
 104 } // End of anonymous namespace
 105
 106 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
 107   return new AMDGPUPassConfig(this, PM);
 108 }
 109
 110 bool
 111 AMDGPUPassConfig::addPreISel()
 112 {
 113   const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
 114   if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
 115     PM->add(createR600KernelParametersPass(
 116                      getAMDGPUTargetMachine().getTargetData()));
 117   }
 118   return false;
 119 }
 120
 121 bool AMDGPUPassConfig::addInstSelector() {
 122   PM->add(createAMDILPeepholeOpt(*TM));
 123   PM->add(createAMDILISelDag(getAMDGPUTargetMachine()));
 124   return false;
 125 }
 126
 127 bool AMDGPUPassConfig::addPreRegAlloc() {
 128   const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
 129
 130   if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
 131     PM->add(createR600LowerInstructionsPass(*TM));
 132   } else {
 133     PM->add(createSILowerShaderInstructionsPass(*TM));
 134     PM->add(createSIAssignInterpRegsPass(*TM));
 135   }
 136   PM->add(createAMDGPULowerInstructionsPass(*TM));
 137   PM->add(createAMDGPUConvertToISAPass(*TM));
 138   return false;
 139 }
 140
 141 bool AMDGPUPassConfig::addPostRegAlloc() {
 142   return false;
 143 }
 144
 145 bool AMDGPUPassConfig::addPreSched2() {
 146   return false;
 147 }
 148
 149 bool AMDGPUPassConfig::addPreEmitPass() {
 150   const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
 151   PM->add(createAMDILCFGPreparationPass(*TM));
 152   PM->add(createAMDILCFGStructurizerPass(*TM));
 153   if (ST.device()->getGeneration() == AMDILDeviceInfo::HD7XXX) {
 154     PM->add(createSIPropagateImmReadsPass(*TM));
 155   }
 156
 157   return false;
 158 }
 159