1 //===-- AMDGPUUtil.cpp - AMDGPU Utility functions -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Common utility functions used by hw codegen targets
12 //===----------------------------------------------------------------------===//
14 #include "AMDGPUUtil.h"
15 #include "AMDGPURegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 // Some instructions act as place holders to emulate operations that the GPU
27 // hardware does automatically. This function can be used to check if
28 // an opcode falls into this category.
29 bool AMDGPU::isPlaceHolderOpcode(unsigned opcode
)
32 default: return false;
34 case AMDGPU::LOAD_INPUT
:
36 case AMDGPU::MASK_WRITE
:
37 case AMDGPU::RESERVE_REG
:
42 bool AMDGPU::isTransOp(unsigned opcode
)
45 default: return false;
47 case AMDGPU::COS_r600
:
50 case AMDGPU::MUL_LIT_r600
:
51 case AMDGPU::MUL_LIT_eg
:
52 case AMDGPU::EXP_IEEE_r600
:
53 case AMDGPU::EXP_IEEE_eg
:
54 case AMDGPU::LOG_CLAMPED_r600
:
55 case AMDGPU::LOG_IEEE_r600
:
56 case AMDGPU::LOG_CLAMPED_eg
:
57 case AMDGPU::LOG_IEEE_eg
:
62 bool AMDGPU::isTexOp(unsigned opcode
)
65 default: return false;
67 case AMDGPU::TEX_GET_TEXTURE_RESINFO
:
68 case AMDGPU::TEX_SAMPLE
:
69 case AMDGPU::TEX_SAMPLE_C
:
70 case AMDGPU::TEX_SAMPLE_L
:
71 case AMDGPU::TEX_SAMPLE_C_L
:
72 case AMDGPU::TEX_SAMPLE_LB
:
73 case AMDGPU::TEX_SAMPLE_C_LB
:
74 case AMDGPU::TEX_SAMPLE_G
:
75 case AMDGPU::TEX_SAMPLE_C_G
:
76 case AMDGPU::TEX_GET_GRADIENTS_H
:
77 case AMDGPU::TEX_GET_GRADIENTS_V
:
78 case AMDGPU::TEX_SET_GRADIENTS_H
:
79 case AMDGPU::TEX_SET_GRADIENTS_V
:
84 bool AMDGPU::isReductionOp(unsigned opcode
)
87 default: return false;
88 case AMDGPU::DOT4_r600
:
94 bool AMDGPU::isCubeOp(unsigned opcode
)
97 default: return false;
98 case AMDGPU::CUBE_r600
:
105 bool AMDGPU::isFCOp(unsigned opcode
)
108 default: return false;
109 case AMDGPU::BREAK_LOGICALZ_f32
:
110 case AMDGPU::BREAK_LOGICALNZ_i32
:
111 case AMDGPU::BREAK_LOGICALZ_i32
:
112 case AMDGPU::BREAK_LOGICALNZ_f32
:
113 case AMDGPU::CONTINUE_LOGICALNZ_f32
:
114 case AMDGPU::IF_LOGICALNZ_i32
:
115 case AMDGPU::IF_LOGICALZ_f32
:
118 case AMDGPU::ENDLOOP
:
119 case AMDGPU::IF_LOGICALNZ_f32
:
120 case AMDGPU::WHILELOOP
:
125 void AMDGPU::utilAddLiveIn(MachineFunction
* MF
,
126 MachineRegisterInfo
& MRI
,
127 const TargetInstrInfo
* TII
,
128 unsigned physReg
, unsigned virtReg
)
130 if (!MRI
.isLiveIn(physReg
)) {
131 MRI
.addLiveIn(physReg
, virtReg
);
132 MF
->front().addLiveIn(physReg
);
133 BuildMI(MF
->front(), MF
->front().begin(), DebugLoc(),
134 TII
->get(TargetOpcode::COPY
), virtReg
)
137 MRI
.replaceRegWith(virtReg
, MRI
.getLiveInVirtReg(physReg
));