src/gallium/drivers/radeon/AMDGPUUtil.cpp

   1 //===-- AMDGPUUtil.cpp - AMDGPU Utility functions -------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Common utility functions used by hw codegen targets
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPUUtil.h"
  15 #include "AMDGPURegisterInfo.h"
  16 #include "AMDIL.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/Target/TargetInstrInfo.h"
  21 #include "llvm/Target/TargetMachine.h"
  22 #include "llvm/Target/TargetRegisterInfo.h"
  23
  24 using namespace llvm;
  25
  26 // Some instructions act as place holders to emulate operations that the GPU
  27 // hardware does automatically. This function can be used to check if
  28 // an opcode falls into this category.
  29 bool AMDGPU::isPlaceHolderOpcode(unsigned opcode)
  30 {
  31   switch (opcode) {
  32   default: return false;
  33   case AMDIL::RETURN:
  34   case AMDIL::LOAD_INPUT:
  35   case AMDIL::LAST:
  36   case AMDIL::MASK_WRITE:
  37   case AMDIL::RESERVE_REG:
  38     return true;
  39   }
  40 }
  41
  42 bool AMDGPU::isTransOp(unsigned opcode)
  43 {
  44   switch(opcode) {
  45     default: return false;
  46
  47     case AMDIL::COS_r600:
  48     case AMDIL::COS_eg:
  49     case AMDIL::RSQ_f32:
  50     case AMDIL::MULLIT:
  51     case AMDIL::MUL_LIT_r600:
  52     case AMDIL::MUL_LIT_eg:
  53     case AMDIL::EXP_IEEE_r600:
  54     case AMDIL::EXP_IEEE_eg:
  55     case AMDIL::LOG_CLAMPED_r600:
  56     case AMDIL::LOG_IEEE_r600:
  57     case AMDIL::LOG_CLAMPED_eg:
  58     case AMDIL::LOG_IEEE_eg:
  59       return true;
  60   }
  61 }
  62
  63 bool AMDGPU::isTexOp(unsigned opcode)
  64 {
  65   switch(opcode) {
  66   default: return false;
  67   case AMDIL::TEX_LD:
  68   case AMDIL::TEX_GET_TEXTURE_RESINFO:
  69   case AMDIL::TEX_SAMPLE:
  70   case AMDIL::TEX_SAMPLE_C:
  71   case AMDIL::TEX_SAMPLE_L:
  72   case AMDIL::TEX_SAMPLE_C_L:
  73   case AMDIL::TEX_SAMPLE_LB:
  74   case AMDIL::TEX_SAMPLE_C_LB:
  75   case AMDIL::TEX_SAMPLE_G:
  76   case AMDIL::TEX_SAMPLE_C_G:
  77   case AMDIL::TEX_GET_GRADIENTS_H:
  78   case AMDIL::TEX_GET_GRADIENTS_V:
  79   case AMDIL::TEX_SET_GRADIENTS_H:
  80   case AMDIL::TEX_SET_GRADIENTS_V:
  81     return true;
  82   }
  83 }
  84
  85 bool AMDGPU::isReductionOp(unsigned opcode)
  86 {
  87   switch(opcode) {
  88     default: return false;
  89     case AMDIL::DOT4_r600:
  90     case AMDIL::DOT4_eg:
  91       return true;
  92   }
  93 }
  94
  95 bool AMDGPU::isCubeOp(unsigned opcode)
  96 {
  97   switch(opcode) {
  98     default: return false;
  99     case AMDIL::CUBE_r600:
 100     case AMDIL::CUBE_eg:
 101       return true;
 102   }
 103 }
 104
 105
 106 bool AMDGPU::isFCOp(unsigned opcode)
 107 {
 108   switch(opcode) {
 109   default: return false;
 110   case AMDIL::BREAK_LOGICALZ_f32:
 111   case AMDIL::BREAK_LOGICALNZ_i32:
 112   case AMDIL::BREAK_LOGICALZ_i32:
 113   case AMDIL::BREAK_LOGICALNZ_f32:
 114   case AMDIL::CONTINUE_LOGICALNZ_f32:
 115   case AMDIL::IF_LOGICALNZ_i32:
 116   case AMDIL::IF_LOGICALZ_f32:
 117   case AMDIL::ELSE:
 118   case AMDIL::ENDIF:
 119   case AMDIL::ENDLOOP:
 120   case AMDIL::IF_LOGICALNZ_f32:
 121   case AMDIL::WHILELOOP:
 122     return true;
 123   }
 124 }
 125
 126 void AMDGPU::utilAddLiveIn(llvm::MachineFunction * MF,
 127                            llvm::MachineRegisterInfo & MRI,
 128                            const llvm::TargetInstrInfo * TII,
 129                            unsigned physReg, unsigned virtReg)
 130 {
 131     if (!MRI.isLiveIn(physReg)) {
 132       MRI.addLiveIn(physReg, virtReg);
 133       MF->front().addLiveIn(physReg);
 134       BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
 135               TII->get(TargetOpcode::COPY), virtReg)
 136                 .addReg(physReg);
 137     } else {
 138       MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
 139     }
 140 }