src/gallium/drivers/radeon/AMDIL.h

   1 //===-- AMDIL.h - Top-level interface for AMDIL representation --*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file contains the entry points for global functions defined in the LLVM
  11 // AMDIL back-end.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDIL_H_
  16 #define AMDIL_H_
  17
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/Target/TargetMachine.h"
  20
  21 #define AMDIL_MAJOR_VERSION 2
  22 #define AMDIL_MINOR_VERSION 0
  23 #define AMDIL_REVISION_NUMBER 74
  24 #define ARENA_SEGMENT_RESERVED_UAVS 12
  25 #define DEFAULT_ARENA_UAV_ID 8
  26 #define DEFAULT_RAW_UAV_ID 7
  27 #define GLOBAL_RETURN_RAW_UAV_ID 11
  28 #define HW_MAX_NUM_CB 8
  29 #define MAX_NUM_UNIQUE_UAVS 8
  30 #define OPENCL_MAX_NUM_ATOMIC_COUNTERS 8
  31 #define OPENCL_MAX_READ_IMAGES 128
  32 #define OPENCL_MAX_WRITE_IMAGES 8
  33 #define OPENCL_MAX_SAMPLERS 16
  34
  35 // The next two values can never be zero, as zero is the ID that is
  36 // used to assert against.
  37 #define DEFAULT_LDS_ID     1
  38 #define DEFAULT_GDS_ID     1
  39 #define DEFAULT_SCRATCH_ID 1
  40 #define DEFAULT_VEC_SLOTS  8
  41
  42 // SC->CAL version matchings.
  43 #define CAL_VERSION_SC_150               1700
  44 #define CAL_VERSION_SC_149               1700
  45 #define CAL_VERSION_SC_148               1525
  46 #define CAL_VERSION_SC_147               1525
  47 #define CAL_VERSION_SC_146               1525
  48 #define CAL_VERSION_SC_145               1451
  49 #define CAL_VERSION_SC_144               1451
  50 #define CAL_VERSION_SC_143               1441
  51 #define CAL_VERSION_SC_142               1441
  52 #define CAL_VERSION_SC_141               1420
  53 #define CAL_VERSION_SC_140               1400
  54 #define CAL_VERSION_SC_139               1387
  55 #define CAL_VERSION_SC_138               1387
  56 #define CAL_APPEND_BUFFER_SUPPORT        1340
  57 #define CAL_VERSION_SC_137               1331
  58 #define CAL_VERSION_SC_136                982
  59 #define CAL_VERSION_SC_135                950
  60 #define CAL_VERSION_GLOBAL_RETURN_BUFFER  990
  61
  62 #define OCL_DEVICE_RV710        0x0001
  63 #define OCL_DEVICE_RV730        0x0002
  64 #define OCL_DEVICE_RV770        0x0004
  65 #define OCL_DEVICE_CEDAR        0x0008
  66 #define OCL_DEVICE_REDWOOD      0x0010
  67 #define OCL_DEVICE_JUNIPER      0x0020
  68 #define OCL_DEVICE_CYPRESS      0x0040
  69 #define OCL_DEVICE_CAICOS       0x0080
  70 #define OCL_DEVICE_TURKS        0x0100
  71 #define OCL_DEVICE_BARTS        0x0200
  72 #define OCL_DEVICE_CAYMAN       0x0400
  73 #define OCL_DEVICE_ALL          0x3FFF
  74
  75 /// The number of function ID's that are reserved for
  76 /// internal compiler usage.
  77 const unsigned int RESERVED_FUNCS = 1024;
  78
  79 #define AMDIL_OPT_LEVEL_DECL
  80 #define  AMDIL_OPT_LEVEL_VAR
  81 #define AMDIL_OPT_LEVEL_VAR_NO_COMMA
  82
  83 namespace llvm {
  84 class AMDILInstrPrinter;
  85 class AMDILTargetMachine;
  86 class FunctionPass;
  87 class MCAsmInfo;
  88 class raw_ostream;
  89 class Target;
  90 class TargetMachine;
  91
  92 /// Instruction selection passes.
  93 FunctionPass*
  94   createAMDILISelDag(AMDILTargetMachine &TM AMDIL_OPT_LEVEL_DECL);
  95 FunctionPass*
  96   createAMDILPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
  97
  98 /// Pre regalloc passes.
  99 FunctionPass*
 100   createAMDILMachinePeephole(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 101
 102 /// Pre emit passes.
 103 FunctionPass*
 104   createAMDILCFGPreparationPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 105 FunctionPass*
 106   createAMDILCFGStructurizerPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 107
 108 extern Target TheAMDILTarget;
 109 extern Target TheAMDGPUTarget;
 110 } // end namespace llvm;
 111
 112 #define GET_REGINFO_ENUM
 113 #include "AMDILGenRegisterInfo.inc"
 114 #define GET_INSTRINFO_ENUM
 115 #include "AMDILGenInstrInfo.inc"
 116
 117 /// Include device information enumerations
 118 #include "AMDILDeviceInfo.h"
 119
 120 namespace llvm {
 121 /// OpenCL uses address spaces to differentiate between
 122 /// various memory regions on the hardware. On the CPU
 123 /// all of the address spaces point to the same memory,
 124 /// however on the GPU, each address space points to
 125 /// a seperate piece of memory that is unique from other
 126 /// memory locations.
 127 namespace AMDILAS {
 128 enum AddressSpaces {
 129   PRIVATE_ADDRESS  = 0, // Address space for private memory.
 130   GLOBAL_ADDRESS   = 1, // Address space for global memory (RAT0, VTX0).
 131   CONSTANT_ADDRESS = 2, // Address space for constant memory.
 132   LOCAL_ADDRESS    = 3, // Address space for local memory.
 133   REGION_ADDRESS   = 4, // Address space for region memory.
 134   ADDRESS_NONE     = 5, // Address space for unknown memory.
 135   PARAM_D_ADDRESS  = 6, // Address space for direct addressible parameter memory (CONST0)
 136   PARAM_I_ADDRESS  = 7, // Address space for indirect addressible parameter memory (VTX1)
 137   LAST_ADDRESS     = 8
 138 };
 139
 140 // This union/struct combination is an easy way to read out the
 141 // exact bits that are needed.
 142 typedef union ResourceRec {
 143   struct {
 144 #ifdef __BIG_ENDIAN__
 145     unsigned short isImage       : 1;  // Reserved for future use/llvm.
 146     unsigned short ResourceID    : 10; // Flag to specify the resourece ID for
 147                                        // the op.
 148     unsigned short HardwareInst  : 1;  // Flag to specify that this instruction
 149                                        // is a hardware instruction.
 150     unsigned short ConflictPtr   : 1;  // Flag to specify that the pointer has a
 151                                        // conflict.
 152     unsigned short ByteStore     : 1;  // Flag to specify if the op is a byte
 153                                        // store op.
 154     unsigned short PointerPath   : 1;  // Flag to specify if the op is on the
 155                                        // pointer path.
 156     unsigned short CacheableRead : 1;  // Flag to specify if the read is
 157                                        // cacheable.
 158 #else
 159     unsigned short CacheableRead : 1;  // Flag to specify if the read is
 160                                        // cacheable.
 161     unsigned short PointerPath   : 1;  // Flag to specify if the op is on the
 162                                        // pointer path.
 163     unsigned short ByteStore     : 1;  // Flag to specify if the op is byte
 164                                        // store op.
 165     unsigned short ConflictPtr   : 1;  // Flag to specify that the pointer has
 166                                        // a conflict.
 167     unsigned short HardwareInst  : 1;  // Flag to specify that this instruction
 168                                        // is a hardware instruction.
 169     unsigned short ResourceID    : 10; // Flag to specify the resource ID for
 170                                        // the op.
 171     unsigned short isImage       : 1;  // Reserved for future use.
 172 #endif
 173   } bits;
 174   unsigned short u16all;
 175 } InstrResEnc;
 176
 177 } // namespace AMDILAS
 178
 179 // Enums corresponding to AMDIL condition codes for IL.  These
 180 // values must be kept in sync with the ones in the .td file.
 181 namespace AMDILCC {
 182 enum CondCodes {
 183   // AMDIL specific condition codes. These correspond to the IL_CC_*
 184   // in AMDILInstrInfo.td and must be kept in the same order.
 185   IL_CC_D_EQ  =  0,   // DEQ instruction.
 186   IL_CC_D_GE  =  1,   // DGE instruction.
 187   IL_CC_D_LT  =  2,   // DLT instruction.
 188   IL_CC_D_NE  =  3,   // DNE instruction.
 189   IL_CC_F_EQ  =  4,   //  EQ instruction.
 190   IL_CC_F_GE  =  5,   //  GE instruction.
 191   IL_CC_F_LT  =  6,   //  LT instruction.
 192   IL_CC_F_NE  =  7,   //  NE instruction.
 193   IL_CC_I_EQ  =  8,   // IEQ instruction.
 194   IL_CC_I_GE  =  9,   // IGE instruction.
 195   IL_CC_I_LT  = 10,   // ILT instruction.
 196   IL_CC_I_NE  = 11,   // INE instruction.
 197   IL_CC_U_GE  = 12,   // UGE instruction.
 198   IL_CC_U_LT  = 13,   // ULE instruction.
 199   // Pseudo IL Comparison instructions here.
 200   IL_CC_F_GT  = 14,   //  GT instruction.
 201   IL_CC_U_GT  = 15,
 202   IL_CC_I_GT  = 16,
 203   IL_CC_D_GT  = 17,
 204   IL_CC_F_LE  = 18,   //  LE instruction
 205   IL_CC_U_LE  = 19,
 206   IL_CC_I_LE  = 20,
 207   IL_CC_D_LE  = 21,
 208   IL_CC_F_UNE = 22,
 209   IL_CC_F_UEQ = 23,
 210   IL_CC_F_ULT = 24,
 211   IL_CC_F_UGT = 25,
 212   IL_CC_F_ULE = 26,
 213   IL_CC_F_UGE = 27,
 214   IL_CC_F_ONE = 28,
 215   IL_CC_F_OEQ = 29,
 216   IL_CC_F_OLT = 30,
 217   IL_CC_F_OGT = 31,
 218   IL_CC_F_OLE = 32,
 219   IL_CC_F_OGE = 33,
 220   IL_CC_D_UNE = 34,
 221   IL_CC_D_UEQ = 35,
 222   IL_CC_D_ULT = 36,
 223   IL_CC_D_UGT = 37,
 224   IL_CC_D_ULE = 38,
 225   IL_CC_D_UGE = 39,
 226   IL_CC_D_ONE = 40,
 227   IL_CC_D_OEQ = 41,
 228   IL_CC_D_OLT = 42,
 229   IL_CC_D_OGT = 43,
 230   IL_CC_D_OLE = 44,
 231   IL_CC_D_OGE = 45,
 232   IL_CC_U_EQ  = 46,
 233   IL_CC_U_NE  = 47,
 234   IL_CC_F_O   = 48,
 235   IL_CC_D_O   = 49,
 236   IL_CC_F_UO  = 50,
 237   IL_CC_D_UO  = 51,
 238   IL_CC_L_LE  = 52,
 239   IL_CC_L_GE  = 53,
 240   IL_CC_L_EQ  = 54,
 241   IL_CC_L_NE  = 55,
 242   IL_CC_L_LT  = 56,
 243   IL_CC_L_GT  = 57,
 244   IL_CC_UL_LE = 58,
 245   IL_CC_UL_GE = 59,
 246   IL_CC_UL_EQ = 60,
 247   IL_CC_UL_NE = 61,
 248   IL_CC_UL_LT = 62,
 249   IL_CC_UL_GT = 63,
 250   COND_ERROR  = 64
 251 };
 252
 253 } // end namespace AMDILCC
 254 } // end namespace llvm
 255 #endif // AMDIL_H_