src/gallium/drivers/radeon/AMDIL.h

   1 //===-- AMDIL.h - Top-level interface for AMDIL representation --*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file contains the entry points for global functions defined in the LLVM
  11 // AMDIL back-end.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDIL_H_
  16 #define AMDIL_H_
  17
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/Target/TargetMachine.h"
  20
  21 #define AMDIL_MAJOR_VERSION 2
  22 #define AMDIL_MINOR_VERSION 0
  23 #define AMDIL_REVISION_NUMBER 74
  24 #define ARENA_SEGMENT_RESERVED_UAVS 12
  25 #define DEFAULT_ARENA_UAV_ID 8
  26 #define DEFAULT_RAW_UAV_ID 7
  27 #define GLOBAL_RETURN_RAW_UAV_ID 11
  28 #define HW_MAX_NUM_CB 8
  29 #define MAX_NUM_UNIQUE_UAVS 8
  30 #define OPENCL_MAX_NUM_ATOMIC_COUNTERS 8
  31 #define OPENCL_MAX_READ_IMAGES 128
  32 #define OPENCL_MAX_WRITE_IMAGES 8
  33 #define OPENCL_MAX_SAMPLERS 16
  34
  35 // The next two values can never be zero, as zero is the ID that is
  36 // used to assert against.
  37 #define DEFAULT_LDS_ID     1
  38 #define DEFAULT_GDS_ID     1
  39 #define DEFAULT_SCRATCH_ID 1
  40 #define DEFAULT_VEC_SLOTS  8
  41
  42 // SC->CAL version matchings.
  43 #define CAL_VERSION_SC_150               1700
  44 #define CAL_VERSION_SC_149               1700
  45 #define CAL_VERSION_SC_148               1525
  46 #define CAL_VERSION_SC_147               1525
  47 #define CAL_VERSION_SC_146               1525
  48 #define CAL_VERSION_SC_145               1451
  49 #define CAL_VERSION_SC_144               1451
  50 #define CAL_VERSION_SC_143               1441
  51 #define CAL_VERSION_SC_142               1441
  52 #define CAL_VERSION_SC_141               1420
  53 #define CAL_VERSION_SC_140               1400
  54 #define CAL_VERSION_SC_139               1387
  55 #define CAL_VERSION_SC_138               1387
  56 #define CAL_APPEND_BUFFER_SUPPORT        1340
  57 #define CAL_VERSION_SC_137               1331
  58 #define CAL_VERSION_SC_136                982
  59 #define CAL_VERSION_SC_135                950
  60 #define CAL_VERSION_GLOBAL_RETURN_BUFFER  990
  61
  62 #define OCL_DEVICE_RV710        0x0001
  63 #define OCL_DEVICE_RV730        0x0002
  64 #define OCL_DEVICE_RV770        0x0004
  65 #define OCL_DEVICE_CEDAR        0x0008
  66 #define OCL_DEVICE_REDWOOD      0x0010
  67 #define OCL_DEVICE_JUNIPER      0x0020
  68 #define OCL_DEVICE_CYPRESS      0x0040
  69 #define OCL_DEVICE_CAICOS       0x0080
  70 #define OCL_DEVICE_TURKS        0x0100
  71 #define OCL_DEVICE_BARTS        0x0200
  72 #define OCL_DEVICE_CAYMAN       0x0400
  73 #define OCL_DEVICE_ALL          0x3FFF
  74
  75 /// The number of function ID's that are reserved for
  76 /// internal compiler usage.
  77 const unsigned int RESERVED_FUNCS = 1024;
  78
  79 #define AMDIL_OPT_LEVEL_DECL
  80 #define  AMDIL_OPT_LEVEL_VAR
  81 #define AMDIL_OPT_LEVEL_VAR_NO_COMMA
  82
  83 namespace llvm {
  84 class AMDILInstrPrinter;
  85 class AMDILTargetMachine;
  86 class FunctionPass;
  87 class MCAsmInfo;
  88 class raw_ostream;
  89 class Target;
  90 class TargetMachine;
  91
  92 /// Instruction selection passes.
  93 FunctionPass*
  94   createAMDILISelDag(AMDILTargetMachine &TM AMDIL_OPT_LEVEL_DECL);
  95 FunctionPass*
  96   createAMDILBarrierDetect(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
  97 FunctionPass*
  98   createAMDILPrintfConvert(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
  99 FunctionPass*
 100   createAMDILInlinePass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 101 FunctionPass*
 102   createAMDILPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 103
 104 /// Pre regalloc passes.
 105 FunctionPass*
 106   createAMDILMachinePeephole(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 107
 108 /// Pre emit passes.
 109 FunctionPass*
 110   createAMDILCFGPreparationPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 111 FunctionPass*
 112   createAMDILCFGStructurizerPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 113 FunctionPass*
 114   createAMDILLiteralManager(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 115 FunctionPass*
 116   createAMDILIOExpansion(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
 117
 118 extern Target TheAMDILTarget;
 119 extern Target TheAMDGPUTarget;
 120 } // end namespace llvm;
 121
 122 #define GET_REGINFO_ENUM
 123 #include "AMDILGenRegisterInfo.inc"
 124 #define GET_INSTRINFO_ENUM
 125 #include "AMDILGenInstrInfo.inc"
 126
 127 /// Include device information enumerations
 128 #include "AMDILDeviceInfo.h"
 129
 130 namespace llvm {
 131 /// OpenCL uses address spaces to differentiate between
 132 /// various memory regions on the hardware. On the CPU
 133 /// all of the address spaces point to the same memory,
 134 /// however on the GPU, each address space points to
 135 /// a seperate piece of memory that is unique from other
 136 /// memory locations.
 137 namespace AMDILAS {
 138 enum AddressSpaces {
 139   PRIVATE_ADDRESS  = 0, // Address space for private memory.
 140   GLOBAL_ADDRESS   = 1, // Address space for global memory (RAT0, VTX0).
 141   CONSTANT_ADDRESS = 2, // Address space for constant memory.
 142   LOCAL_ADDRESS    = 3, // Address space for local memory.
 143   REGION_ADDRESS   = 4, // Address space for region memory.
 144   ADDRESS_NONE     = 5, // Address space for unknown memory.
 145   PARAM_D_ADDRESS  = 6, // Address space for direct addressible parameter memory (CONST0)
 146   PARAM_I_ADDRESS  = 7, // Address space for indirect addressible parameter memory (VTX1)
 147   LAST_ADDRESS     = 8
 148 };
 149
 150 // We are piggybacking on the CommentFlag enum in MachineInstr.h to
 151 // set bits in AsmPrinterFlags of the MachineInstruction. We will
 152 // start at bit 16 and allocate down while LLVM will start at bit
 153 // 1 and allocate up.
 154
 155 // This union/struct combination is an easy way to read out the
 156 // exact bits that are needed.
 157 typedef union ResourceRec {
 158   struct {
 159 #ifdef __BIG_ENDIAN__
 160     unsigned short isImage       : 1;  // Reserved for future use/llvm.
 161     unsigned short ResourceID    : 10; // Flag to specify the resourece ID for
 162                                        // the op.
 163     unsigned short HardwareInst  : 1;  // Flag to specify that this instruction
 164                                        // is a hardware instruction.
 165     unsigned short ConflictPtr   : 1;  // Flag to specify that the pointer has a
 166                                        // conflict.
 167     unsigned short ByteStore     : 1;  // Flag to specify if the op is a byte
 168                                        // store op.
 169     unsigned short PointerPath   : 1;  // Flag to specify if the op is on the
 170                                        // pointer path.
 171     unsigned short CacheableRead : 1;  // Flag to specify if the read is
 172                                        // cacheable.
 173 #else
 174     unsigned short CacheableRead : 1;  // Flag to specify if the read is
 175                                        // cacheable.
 176     unsigned short PointerPath   : 1;  // Flag to specify if the op is on the
 177                                        // pointer path.
 178     unsigned short ByteStore     : 1;  // Flag to specify if the op is byte
 179                                        // store op.
 180     unsigned short ConflictPtr   : 1;  // Flag to specify that the pointer has
 181                                        // a conflict.
 182     unsigned short HardwareInst  : 1;  // Flag to specify that this instruction
 183                                        // is a hardware instruction.
 184     unsigned short ResourceID    : 10; // Flag to specify the resource ID for
 185                                        // the op.
 186     unsigned short isImage       : 1;  // Reserved for future use.
 187 #endif
 188   } bits;
 189   unsigned short u16all;
 190 } InstrResEnc;
 191
 192 } // namespace AMDILAS
 193
 194 // The OpSwizzle encodes a subset of all possible
 195 // swizzle combinations into a number of bits using
 196 // only the combinations utilized by the backend.
 197 // The lower 128 are for source swizzles and the
 198 // upper 128 or for destination swizzles.
 199 // The valid mappings can be found in the
 200 // getSrcSwizzle and getDstSwizzle functions of
 201 // AMDILUtilityFunctions.cpp.
 202 typedef union SwizzleRec {
 203   struct {
 204 #ifdef __BIG_ENDIAN__
 205     unsigned char dst : 1;
 206     unsigned char swizzle : 7;
 207 #else
 208     unsigned char swizzle : 7;
 209     unsigned char dst : 1;
 210 #endif
 211   } bits;
 212   unsigned char u8all;
 213 } OpSwizzle;
 214 // Enums corresponding to AMDIL condition codes for IL.  These
 215 // values must be kept in sync with the ones in the .td file.
 216 namespace AMDILCC {
 217 enum CondCodes {
 218   // AMDIL specific condition codes. These correspond to the IL_CC_*
 219   // in AMDILInstrInfo.td and must be kept in the same order.
 220   IL_CC_D_EQ  =  0,   // DEQ instruction.
 221   IL_CC_D_GE  =  1,   // DGE instruction.
 222   IL_CC_D_LT  =  2,   // DLT instruction.
 223   IL_CC_D_NE  =  3,   // DNE instruction.
 224   IL_CC_F_EQ  =  4,   //  EQ instruction.
 225   IL_CC_F_GE  =  5,   //  GE instruction.
 226   IL_CC_F_LT  =  6,   //  LT instruction.
 227   IL_CC_F_NE  =  7,   //  NE instruction.
 228   IL_CC_I_EQ  =  8,   // IEQ instruction.
 229   IL_CC_I_GE  =  9,   // IGE instruction.
 230   IL_CC_I_LT  = 10,   // ILT instruction.
 231   IL_CC_I_NE  = 11,   // INE instruction.
 232   IL_CC_U_GE  = 12,   // UGE instruction.
 233   IL_CC_U_LT  = 13,   // ULE instruction.
 234   // Pseudo IL Comparison instructions here.
 235   IL_CC_F_GT  = 14,   //  GT instruction.
 236   IL_CC_U_GT  = 15,
 237   IL_CC_I_GT  = 16,
 238   IL_CC_D_GT  = 17,
 239   IL_CC_F_LE  = 18,   //  LE instruction
 240   IL_CC_U_LE  = 19,
 241   IL_CC_I_LE  = 20,
 242   IL_CC_D_LE  = 21,
 243   IL_CC_F_UNE = 22,
 244   IL_CC_F_UEQ = 23,
 245   IL_CC_F_ULT = 24,
 246   IL_CC_F_UGT = 25,
 247   IL_CC_F_ULE = 26,
 248   IL_CC_F_UGE = 27,
 249   IL_CC_F_ONE = 28,
 250   IL_CC_F_OEQ = 29,
 251   IL_CC_F_OLT = 30,
 252   IL_CC_F_OGT = 31,
 253   IL_CC_F_OLE = 32,
 254   IL_CC_F_OGE = 33,
 255   IL_CC_D_UNE = 34,
 256   IL_CC_D_UEQ = 35,
 257   IL_CC_D_ULT = 36,
 258   IL_CC_D_UGT = 37,
 259   IL_CC_D_ULE = 38,
 260   IL_CC_D_UGE = 39,
 261   IL_CC_D_ONE = 40,
 262   IL_CC_D_OEQ = 41,
 263   IL_CC_D_OLT = 42,
 264   IL_CC_D_OGT = 43,
 265   IL_CC_D_OLE = 44,
 266   IL_CC_D_OGE = 45,
 267   IL_CC_U_EQ  = 46,
 268   IL_CC_U_NE  = 47,
 269   IL_CC_F_O   = 48,
 270   IL_CC_D_O   = 49,
 271   IL_CC_F_UO  = 50,
 272   IL_CC_D_UO  = 51,
 273   IL_CC_L_LE  = 52,
 274   IL_CC_L_GE  = 53,
 275   IL_CC_L_EQ  = 54,
 276   IL_CC_L_NE  = 55,
 277   IL_CC_L_LT  = 56,
 278   IL_CC_L_GT  = 57,
 279   IL_CC_UL_LE = 58,
 280   IL_CC_UL_GE = 59,
 281   IL_CC_UL_EQ = 60,
 282   IL_CC_UL_NE = 61,
 283   IL_CC_UL_LT = 62,
 284   IL_CC_UL_GT = 63,
 285   COND_ERROR  = 64
 286 };
 287
 288 } // end namespace AMDILCC
 289 } // end namespace llvm
 290 #endif // AMDIL_H_