radeon/llvm: Move lowering of SETCC node to R600ISelLowering
[mesa.git] / src / gallium / drivers / radeon / AMDILCallingConv.td
1 //===- AMDILCallingConv.td - Calling Conventions AMDIL -----*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9 //
10 // This describes the calling conventions for the AMDIL architectures.
11 //
12 //===----------------------------------------------------------------------===//
13
14 //===----------------------------------------------------------------------===//
15 // Return Value Calling Conventions
16 //===----------------------------------------------------------------------===//
17
18 // AMDIL 32-bit C return-value convention.
19 def RetCC_AMDIL32 : CallingConv<[
20 // Since IL has no return values, all values can be emulated on the stack
21 // The stack can then be mapped to a number of sequential virtual registers
22 // in IL
23
24 // Integer and FP scalar values get put on the stack at 16-byte alignment
25 // but with a size of 4 bytes
26 CCIfType<[i32, f32], CCAssignToReg<
27 [
28 R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20
29 ]> >, CCAssignToStack<16, 16>]>;
30
31 // AMDIL 32-bit C Calling convention.
32 def CC_AMDIL32 : CallingConv<[
33 // Since IL has parameter values, all values can be emulated on the stack
34 // The stack can then be mapped to a number of sequential virtual registers
35 // in IL
36 // Integer and FP scalar values get put on the stack at 16-byte alignment
37 // but with a size of 4 bytes
38 // Integer and FP scalar values get put on the stack at 16-byte alignment
39 // but with a size of 4 bytes
40 CCIfType<[i32, f32], CCAssignToReg<
41 [R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20
42 ]> >, CCAssignToStack<16, 16>]>;