src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp

   1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file defines an instruction selector for the AMDIL target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13 #include "AMDGPUISelLowering.h" // For AMDGPUISD
  14 #include "AMDILDevices.h"
  15 #include "AMDILUtilityFunctions.h"
  16 #include "llvm/ADT/ValueMap.h"
  17 #include "llvm/CodeGen/PseudoSourceValue.h"
  18 #include "llvm/CodeGen/SelectionDAGISel.h"
  19 #include "llvm/Support/Compiler.h"
  20 #include <list>
  21 #include <queue>
  22
  23 using namespace llvm;
  24
  25 //===----------------------------------------------------------------------===//
  26 // Instruction Selector Implementation
  27 //===----------------------------------------------------------------------===//
  28
  29 //===----------------------------------------------------------------------===//
  30 // AMDILDAGToDAGISel - AMDIL specific code to select AMDIL machine instructions
  31 // //for SelectionDAG operations.
  32 //
  33 namespace {
  34 class AMDILDAGToDAGISel : public SelectionDAGISel {
  35   // Subtarget - Keep a pointer to the AMDIL Subtarget around so that we can
  36   // make the right decision when generating code for different targets.
  37   const AMDILSubtarget &Subtarget;
  38 public:
  39   AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
  40   virtual ~AMDILDAGToDAGISel();
  41
  42   SDNode *Select(SDNode *N);
  43   virtual const char *getPassName() const;
  44
  45 private:
  46   inline SDValue getSmallIPtrImm(unsigned Imm);
  47
  48   // Complex pattern selectors
  49   bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
  50   bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
  51   bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
  52
  53   static bool checkType(const Value *ptr, unsigned int addrspace);
  54   static const Value *getBasePointerValue(const Value *V);
  55
  56   static bool isGlobalStore(const StoreSDNode *N);
  57   static bool isPrivateStore(const StoreSDNode *N);
  58   static bool isLocalStore(const StoreSDNode *N);
  59   static bool isRegionStore(const StoreSDNode *N);
  60
  61   static bool isCPLoad(const LoadSDNode *N);
  62   static bool isConstantLoad(const LoadSDNode *N, int cbID);
  63   static bool isGlobalLoad(const LoadSDNode *N);
  64   static bool isPrivateLoad(const LoadSDNode *N);
  65   static bool isLocalLoad(const LoadSDNode *N);
  66   static bool isRegionLoad(const LoadSDNode *N);
  67
  68   SDNode *xformAtomicInst(SDNode *N);
  69
  70   bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
  71   bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
  72
  73   // Include the pieces autogenerated from the target description.
  74 #include "AMDGPUGenDAGISel.inc"
  75 };
  76 }  // end anonymous namespace
  77
  78 // createAMDILISelDag - This pass converts a legalized DAG into a AMDIL-specific
  79 // DAG, ready for instruction scheduling.
  80 //
  81 FunctionPass *llvm::createAMDILISelDag(TargetMachine &TM
  82                                         AMDIL_OPT_LEVEL_DECL) {
  83   return new AMDILDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR);
  84 }
  85
  86 AMDILDAGToDAGISel::AMDILDAGToDAGISel(TargetMachine &TM
  87                                       AMDIL_OPT_LEVEL_DECL)
  88   : SelectionDAGISel(TM AMDIL_OPT_LEVEL_VAR), Subtarget(TM.getSubtarget<AMDILSubtarget>())
  89 {
  90 }
  91
  92 AMDILDAGToDAGISel::~AMDILDAGToDAGISel() {
  93 }
  94
  95 SDValue AMDILDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
  96   return CurDAG->getTargetConstant(Imm, MVT::i32);
  97 }
  98
  99 bool AMDILDAGToDAGISel::SelectADDRParam(
 100     SDValue Addr, SDValue& R1, SDValue& R2) {
 101
 102   if (Addr.getOpcode() == ISD::FrameIndex) {
 103     if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
 104       R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
 105       R2 = CurDAG->getTargetConstant(0, MVT::i32);
 106     } else {
 107       R1 = Addr;
 108       R2 = CurDAG->getTargetConstant(0, MVT::i32);
 109     }
 110   } else if (Addr.getOpcode() == ISD::ADD) {
 111     R1 = Addr.getOperand(0);
 112     R2 = Addr.getOperand(1);
 113   } else {
 114     R1 = Addr;
 115     R2 = CurDAG->getTargetConstant(0, MVT::i32);
 116   }
 117   return true;
 118 }
 119
 120 bool AMDILDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
 121   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
 122       Addr.getOpcode() == ISD::TargetGlobalAddress) {
 123     return false;
 124   }
 125   return SelectADDRParam(Addr, R1, R2);
 126 }
 127
 128
 129 bool AMDILDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
 130   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
 131       Addr.getOpcode() == ISD::TargetGlobalAddress) {
 132     return false;
 133   }
 134
 135   if (Addr.getOpcode() == ISD::FrameIndex) {
 136     if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
 137       R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
 138       R2 = CurDAG->getTargetConstant(0, MVT::i64);
 139     } else {
 140       R1 = Addr;
 141       R2 = CurDAG->getTargetConstant(0, MVT::i64);
 142     }
 143   } else if (Addr.getOpcode() == ISD::ADD) {
 144     R1 = Addr.getOperand(0);
 145     R2 = Addr.getOperand(1);
 146   } else {
 147     R1 = Addr;
 148     R2 = CurDAG->getTargetConstant(0, MVT::i64);
 149   }
 150   return true;
 151 }
 152
 153 SDNode *AMDILDAGToDAGISel::Select(SDNode *N) {
 154   unsigned int Opc = N->getOpcode();
 155   if (N->isMachineOpcode()) {
 156     return NULL;   // Already selected.
 157   }
 158   switch (Opc) {
 159   default: break;
 160   case ISD::FrameIndex:
 161     {
 162       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
 163         unsigned int FI = FIN->getIndex();
 164         EVT OpVT = N->getValueType(0);
 165         unsigned int NewOpc = AMDIL::MOVE_i32;
 166         SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
 167         return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
 168       }
 169     }
 170     break;
 171   }
 172   // For all atomic instructions, we need to add a constant
 173   // operand that stores the resource ID in the instruction
 174   if (Opc > AMDILISD::ADDADDR && Opc < AMDILISD::APPEND_ALLOC) {
 175     N = xformAtomicInst(N);
 176   }
 177   return SelectCode(N);
 178 }
 179
 180 bool AMDILDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
 181   if (!ptr) {
 182     return false;
 183   }
 184   Type *ptrType = ptr->getType();
 185   return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
 186 }
 187
 188 const Value * AMDILDAGToDAGISel::getBasePointerValue(const Value *V)
 189 {
 190   if (!V) {
 191     return NULL;
 192   }
 193   const Value *ret = NULL;
 194   ValueMap<const Value *, bool> ValueBitMap;
 195   std::queue<const Value *, std::list<const Value *> > ValueQueue;
 196   ValueQueue.push(V);
 197   while (!ValueQueue.empty()) {
 198     V = ValueQueue.front();
 199     if (ValueBitMap.find(V) == ValueBitMap.end()) {
 200       ValueBitMap[V] = true;
 201       if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
 202         ret = V;
 203         break;
 204       } else if (dyn_cast<GlobalVariable>(V)) {
 205         ret = V;
 206         break;
 207       } else if (dyn_cast<Constant>(V)) {
 208         const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
 209         if (CE) {
 210           ValueQueue.push(CE->getOperand(0));
 211         }
 212       } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
 213         ret = AI;
 214         break;
 215       } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
 216         uint32_t numOps = I->getNumOperands();
 217         for (uint32_t x = 0; x < numOps; ++x) {
 218           ValueQueue.push(I->getOperand(x));
 219         }
 220       } else {
 221         // assert(0 && "Found a Value that we didn't know how to handle!");
 222       }
 223     }
 224     ValueQueue.pop();
 225   }
 226   return ret;
 227 }
 228
 229 bool AMDILDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
 230   return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS);
 231 }
 232
 233 bool AMDILDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
 234   return (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS)
 235           && !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS)
 236           && !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS));
 237 }
 238
 239 bool AMDILDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
 240   return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS);
 241 }
 242
 243 bool AMDILDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
 244   return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS);
 245 }
 246
 247 bool AMDILDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
 248   if (checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)) {
 249     return true;
 250   }
 251   MachineMemOperand *MMO = N->getMemOperand();
 252   const Value *V = MMO->getValue();
 253   const Value *BV = getBasePointerValue(V);
 254   if (MMO
 255       && MMO->getValue()
 256       && ((V && dyn_cast<GlobalValue>(V))
 257           || (BV && dyn_cast<GlobalValue>(
 258                         getBasePointerValue(MMO->getValue()))))) {
 259     return checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS);
 260   } else {
 261     return false;
 262   }
 263 }
 264
 265 bool AMDILDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
 266   return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS);
 267 }
 268
 269 bool AMDILDAGToDAGISel::isLocalLoad(const  LoadSDNode *N) {
 270   return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS);
 271 }
 272
 273 bool AMDILDAGToDAGISel::isRegionLoad(const  LoadSDNode *N) {
 274   return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS);
 275 }
 276
 277 bool AMDILDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
 278   MachineMemOperand *MMO = N->getMemOperand();
 279   if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) {
 280     if (MMO) {
 281       const Value *V = MMO->getValue();
 282       const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
 283       if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
 284         return true;
 285       }
 286     }
 287   }
 288   return false;
 289 }
 290
 291 bool AMDILDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
 292   if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) {
 293     // Check to make sure we are not a constant pool load or a constant load
 294     // that is marked as a private load
 295     if (isCPLoad(N) || isConstantLoad(N, -1)) {
 296       return false;
 297     }
 298   }
 299   if (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS)
 300       && !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS)
 301       && !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS)
 302       && !checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)
 303       && !checkType(N->getSrcValue(), AMDILAS::PARAM_D_ADDRESS)
 304       && !checkType(N->getSrcValue(), AMDILAS::PARAM_I_ADDRESS))
 305   {
 306     return true;
 307   }
 308   return false;
 309 }
 310
 311 const char *AMDILDAGToDAGISel::getPassName() const {
 312   return "AMDIL DAG->DAG Pattern Instruction Selection";
 313 }
 314
 315 SDNode*
 316 AMDILDAGToDAGISel::xformAtomicInst(SDNode *N)
 317 {
 318   uint32_t addVal = 1;
 319   bool addOne = false;
 320   // bool bitCastToInt = (N->getValueType(0) == MVT::f32);
 321   unsigned opc = N->getOpcode();
 322   switch (opc) {
 323     default: return N;
 324     case AMDILISD::ATOM_G_ADD:
 325     case AMDILISD::ATOM_G_AND:
 326     case AMDILISD::ATOM_G_MAX:
 327     case AMDILISD::ATOM_G_UMAX:
 328     case AMDILISD::ATOM_G_MIN:
 329     case AMDILISD::ATOM_G_UMIN:
 330     case AMDILISD::ATOM_G_OR:
 331     case AMDILISD::ATOM_G_SUB:
 332     case AMDILISD::ATOM_G_RSUB:
 333     case AMDILISD::ATOM_G_XCHG:
 334     case AMDILISD::ATOM_G_XOR:
 335     case AMDILISD::ATOM_G_ADD_NORET:
 336     case AMDILISD::ATOM_G_AND_NORET:
 337     case AMDILISD::ATOM_G_MAX_NORET:
 338     case AMDILISD::ATOM_G_UMAX_NORET:
 339     case AMDILISD::ATOM_G_MIN_NORET:
 340     case AMDILISD::ATOM_G_UMIN_NORET:
 341     case AMDILISD::ATOM_G_OR_NORET:
 342     case AMDILISD::ATOM_G_SUB_NORET:
 343     case AMDILISD::ATOM_G_RSUB_NORET:
 344     case AMDILISD::ATOM_G_XCHG_NORET:
 345     case AMDILISD::ATOM_G_XOR_NORET:
 346     case AMDILISD::ATOM_L_ADD:
 347     case AMDILISD::ATOM_L_AND:
 348     case AMDILISD::ATOM_L_MAX:
 349     case AMDILISD::ATOM_L_UMAX:
 350     case AMDILISD::ATOM_L_MIN:
 351     case AMDILISD::ATOM_L_UMIN:
 352     case AMDILISD::ATOM_L_OR:
 353     case AMDILISD::ATOM_L_SUB:
 354     case AMDILISD::ATOM_L_RSUB:
 355     case AMDILISD::ATOM_L_XCHG:
 356     case AMDILISD::ATOM_L_XOR:
 357     case AMDILISD::ATOM_L_ADD_NORET:
 358     case AMDILISD::ATOM_L_AND_NORET:
 359     case AMDILISD::ATOM_L_MAX_NORET:
 360     case AMDILISD::ATOM_L_UMAX_NORET:
 361     case AMDILISD::ATOM_L_MIN_NORET:
 362     case AMDILISD::ATOM_L_UMIN_NORET:
 363     case AMDILISD::ATOM_L_OR_NORET:
 364     case AMDILISD::ATOM_L_SUB_NORET:
 365     case AMDILISD::ATOM_L_RSUB_NORET:
 366     case AMDILISD::ATOM_L_XCHG_NORET:
 367     case AMDILISD::ATOM_L_XOR_NORET:
 368     case AMDILISD::ATOM_R_ADD:
 369     case AMDILISD::ATOM_R_AND:
 370     case AMDILISD::ATOM_R_MAX:
 371     case AMDILISD::ATOM_R_UMAX:
 372     case AMDILISD::ATOM_R_MIN:
 373     case AMDILISD::ATOM_R_UMIN:
 374     case AMDILISD::ATOM_R_OR:
 375     case AMDILISD::ATOM_R_SUB:
 376     case AMDILISD::ATOM_R_RSUB:
 377     case AMDILISD::ATOM_R_XCHG:
 378     case AMDILISD::ATOM_R_XOR:
 379     case AMDILISD::ATOM_R_ADD_NORET:
 380     case AMDILISD::ATOM_R_AND_NORET:
 381     case AMDILISD::ATOM_R_MAX_NORET:
 382     case AMDILISD::ATOM_R_UMAX_NORET:
 383     case AMDILISD::ATOM_R_MIN_NORET:
 384     case AMDILISD::ATOM_R_UMIN_NORET:
 385     case AMDILISD::ATOM_R_OR_NORET:
 386     case AMDILISD::ATOM_R_SUB_NORET:
 387     case AMDILISD::ATOM_R_RSUB_NORET:
 388     case AMDILISD::ATOM_R_XCHG_NORET:
 389     case AMDILISD::ATOM_R_XOR_NORET:
 390     case AMDILISD::ATOM_G_CMPXCHG:
 391     case AMDILISD::ATOM_G_CMPXCHG_NORET:
 392     case AMDILISD::ATOM_L_CMPXCHG:
 393     case AMDILISD::ATOM_L_CMPXCHG_NORET:
 394     case AMDILISD::ATOM_R_CMPXCHG:
 395     case AMDILISD::ATOM_R_CMPXCHG_NORET:
 396              break;
 397     case AMDILISD::ATOM_G_DEC:
 398              addOne = true;
 399              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 400                addVal = (uint32_t)-1;
 401              } else {
 402                opc = AMDILISD::ATOM_G_SUB;
 403              }
 404              break;
 405     case AMDILISD::ATOM_G_INC:
 406              addOne = true;
 407              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 408                addVal = (uint32_t)-1;
 409              } else {
 410                opc = AMDILISD::ATOM_G_ADD;
 411              }
 412              break;
 413     case AMDILISD::ATOM_G_DEC_NORET:
 414              addOne = true;
 415              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 416                addVal = (uint32_t)-1;
 417              } else {
 418                opc = AMDILISD::ATOM_G_SUB_NORET;
 419              }
 420              break;
 421     case AMDILISD::ATOM_G_INC_NORET:
 422              addOne = true;
 423              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 424                addVal = (uint32_t)-1;
 425              } else {
 426                opc = AMDILISD::ATOM_G_ADD_NORET;
 427              }
 428              break;
 429     case AMDILISD::ATOM_L_DEC:
 430              addOne = true;
 431              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 432                addVal = (uint32_t)-1;
 433              } else {
 434                opc = AMDILISD::ATOM_L_SUB;
 435              }
 436              break;
 437     case AMDILISD::ATOM_L_INC:
 438              addOne = true;
 439              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 440                addVal = (uint32_t)-1;
 441              } else {
 442                opc = AMDILISD::ATOM_L_ADD;
 443              }
 444              break;
 445     case AMDILISD::ATOM_L_DEC_NORET:
 446              addOne = true;
 447              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 448                addVal = (uint32_t)-1;
 449              } else {
 450                opc = AMDILISD::ATOM_L_SUB_NORET;
 451              }
 452              break;
 453     case AMDILISD::ATOM_L_INC_NORET:
 454              addOne = true;
 455              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 456                addVal = (uint32_t)-1;
 457              } else {
 458                opc = AMDILISD::ATOM_L_ADD_NORET;
 459              }
 460              break;
 461     case AMDILISD::ATOM_R_DEC:
 462              addOne = true;
 463              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 464                addVal = (uint32_t)-1;
 465              } else {
 466                opc = AMDILISD::ATOM_R_SUB;
 467              }
 468              break;
 469     case AMDILISD::ATOM_R_INC:
 470              addOne = true;
 471              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 472                addVal = (uint32_t)-1;
 473              } else {
 474                opc = AMDILISD::ATOM_R_ADD;
 475              }
 476              break;
 477     case AMDILISD::ATOM_R_DEC_NORET:
 478              addOne = true;
 479              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 480                addVal = (uint32_t)-1;
 481              } else {
 482                opc = AMDILISD::ATOM_R_SUB;
 483              }
 484              break;
 485     case AMDILISD::ATOM_R_INC_NORET:
 486              addOne = true;
 487              if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
 488                addVal = (uint32_t)-1;
 489              } else {
 490                opc = AMDILISD::ATOM_R_ADD_NORET;
 491              }
 492              break;
 493   }
 494   // The largest we can have is a cmpxchg w/ a return value and an output chain.
 495   // The cmpxchg function has 3 inputs and a single output along with an
 496   // output change and a target constant, giving a total of 6.
 497   SDValue Ops[12];
 498   unsigned x = 0;
 499   unsigned y = N->getNumOperands();
 500   for (x = 0; x < y; ++x) {
 501     Ops[x] = N->getOperand(x);
 502   }
 503   if (addOne) {
 504     Ops[x++] = SDValue(SelectCode(CurDAG->getConstant(addVal, MVT::i32).getNode()), 0);
 505   }
 506   Ops[x++] = CurDAG->getTargetConstant(0, MVT::i32);
 507   SDVTList Tys = N->getVTList();
 508   MemSDNode *MemNode = dyn_cast<MemSDNode>(N);
 509   assert(MemNode && "Atomic should be of MemSDNode type!");
 510   N = CurDAG->getMemIntrinsicNode(opc, N->getDebugLoc(), Tys, Ops, x,
 511       MemNode->getMemoryVT(), MemNode->getMemOperand()).getNode();
 512   return N;
 513 }
 514
 515 #ifdef DEBUGTMP
 516 #undef INT64_C
 517 #endif
 518 #undef DEBUGTMP
 519
 520 ///==== AMDGPU Functions ====///
 521
 522 bool AMDILDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
 523                                              SDValue& Offset) {
 524   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
 525       Addr.getOpcode() == ISD::TargetGlobalAddress) {
 526     return false;
 527   }
 528
 529
 530   if (Addr.getOpcode() == ISD::ADD) {
 531     bool Match = false;
 532
 533     // Find the base ptr and the offset
 534     for (unsigned i = 0; i < Addr.getNumOperands(); i++) {
 535       SDValue Arg = Addr.getOperand(i);
 536       ConstantSDNode * OffsetNode = dyn_cast<ConstantSDNode>(Arg);
 537       // This arg isn't a constant so it must be the base PTR.
 538       if (!OffsetNode) {
 539         Base = Addr.getOperand(i);
 540         continue;
 541       }
 542       // Check if the constant argument fits in 8-bits.  The offset is in bytes
 543       // so we need to convert it to dwords.
 544       if (isInt<8>(OffsetNode->getZExtValue() >> 2)) {
 545         Match = true;
 546         Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2,
 547                                            MVT::i32);
 548       }
 549     }
 550     return Match;
 551   }
 552
 553   // Default case, no offset
 554   Base = Addr;
 555   Offset = CurDAG->getTargetConstant(0, MVT::i32);
 556   return true;
 557 }
 558
 559 bool AMDILDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
 560                                       SDValue& Offset) {
 561   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
 562       Addr.getOpcode() == ISD::TargetGlobalAddress  ||
 563       Addr.getOpcode() != ISD::ADD) {
 564     return false;
 565   }
 566
 567   Base = Addr.getOperand(0);
 568   Offset = Addr.getOperand(1);
 569
 570   return false;
 571 }