src/gallium/drivers/radeon/AMDILISelLowering.h

   1 //===-- AMDILISelLowering.h - AMDIL DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that AMDIL uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDIL_ISELLOWERING_H_
  16 #define AMDIL_ISELLOWERING_H_
  17 #include "AMDIL.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21 #include "llvm/Target/TargetLowering.h"
  22
  23 namespace llvm
  24 {
  25   namespace AMDILISD
  26   {
  27     enum
  28     {
  29       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  30       CMOVLOG,     // 32bit FP Conditional move logical instruction
  31       MAD,         // 32bit Fused Multiply Add instruction
  32       VBUILD,      // scalar to vector mov instruction
  33       CALL,        // Function call based on a single integer
  34       SELECT_CC,   // Select the correct conditional instruction
  35       UMUL,        // 32bit unsigned multiplication
  36       DIV_INF,      // Divide with infinity returned on zero divisor
  37       CMP,
  38       IL_CC_I_GT,
  39       IL_CC_I_LT,
  40       IL_CC_I_GE,
  41       IL_CC_I_LE,
  42       IL_CC_I_EQ,
  43       IL_CC_I_NE,
  44       RET_FLAG,
  45       BRANCH_COND,
  46       LAST_ISD_NUMBER
  47     };
  48   } // AMDILISD
  49
  50   class MachineBasicBlock;
  51   class MachineInstr;
  52   class DebugLoc;
  53   class TargetInstrInfo;
  54
  55   class AMDILTargetLowering : public TargetLowering
  56   {
  57     public:
  58       AMDILTargetLowering(TargetMachine &TM);
  59
  60       virtual SDValue
  61         LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  62
  63       /// computeMaskedBitsForTargetNode - Determine which of
  64       /// the bits specified
  65       /// in Mask are known to be either zero or one and return them in
  66       /// the
  67       /// KnownZero/KnownOne bitsets.
  68       virtual void
  69         computeMaskedBitsForTargetNode(
  70             const SDValue Op,
  71             APInt &KnownZero,
  72             APInt &KnownOne,
  73             const SelectionDAG &DAG,
  74             unsigned Depth = 0
  75             ) const;
  76
  77       virtual bool
  78         getTgtMemIntrinsic(IntrinsicInfo &Info,
  79                                   const CallInst &I, unsigned Intrinsic) const;
  80       virtual const char*
  81         getTargetNodeName(
  82             unsigned Opcode
  83             ) const;
  84       // We want to mark f32/f64 floating point values as
  85       // legal
  86       bool
  87         isFPImmLegal(const APFloat &Imm, EVT VT) const;
  88       // We don't want to shrink f64/f32 constants because
  89       // they both take up the same amount of space and
  90       // we don't want to use a f2d instruction.
  91       bool ShouldShrinkFPConstant(EVT VT) const;
  92
  93       /// getFunctionAlignment - Return the Log2 alignment of this
  94       /// function.
  95       virtual unsigned int
  96         getFunctionAlignment(const Function *F) const;
  97
  98     private:
  99       CCAssignFn*
 100         CCAssignFnForNode(unsigned int CC) const;
 101
 102       SDValue LowerCallResult(SDValue Chain,
 103           SDValue InFlag,
 104           CallingConv::ID CallConv,
 105           bool isVarArg,
 106           const SmallVectorImpl<ISD::InputArg> &Ins,
 107           DebugLoc dl,
 108           SelectionDAG &DAG,
 109           SmallVectorImpl<SDValue> &InVals) const;
 110
 111       SDValue LowerMemArgument(SDValue Chain,
 112           CallingConv::ID CallConv,
 113           const SmallVectorImpl<ISD::InputArg> &ArgInfo,
 114           DebugLoc dl, SelectionDAG &DAG,
 115           const CCValAssign &VA,  MachineFrameInfo *MFI,
 116           unsigned i) const;
 117
 118       SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
 119           SDValue Arg,
 120           DebugLoc dl, SelectionDAG &DAG,
 121           const CCValAssign &VA,
 122           ISD::ArgFlagsTy Flags) const;
 123
 124       virtual SDValue
 125         LowerFormalArguments(SDValue Chain,
 126             CallingConv::ID CallConv, bool isVarArg,
 127             const SmallVectorImpl<ISD::InputArg> &Ins,
 128             DebugLoc dl, SelectionDAG &DAG,
 129             SmallVectorImpl<SDValue> &InVals) const;
 130
 131       virtual SDValue
 132         LowerCall(SDValue Chain, SDValue Callee,
 133             CallingConv::ID CallConv, bool isVarArg, bool doesNotRet,
 134             bool &isTailCall,
 135             const SmallVectorImpl<ISD::OutputArg> &Outs,
 136             const SmallVectorImpl<SDValue> &OutVals,
 137             const SmallVectorImpl<ISD::InputArg> &Ins,
 138             DebugLoc dl, SelectionDAG &DAG,
 139             SmallVectorImpl<SDValue> &InVals) const;
 140
 141       virtual SDValue
 142         LowerReturn(SDValue Chain,
 143             CallingConv::ID CallConv, bool isVarArg,
 144             const SmallVectorImpl<ISD::OutputArg> &Outs,
 145             const SmallVectorImpl<SDValue> &OutVals,
 146             DebugLoc dl, SelectionDAG &DAG) const;
 147
 148       SDValue
 149         LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 150
 151       SDValue
 152         LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 153
 154       SDValue
 155         LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 156
 157       SDValue
 158         LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
 159
 160       SDValue
 161         LowerSREM(SDValue Op, SelectionDAG &DAG) const;
 162       SDValue
 163         LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
 164       SDValue
 165         LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
 166       SDValue
 167         LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
 168       SDValue
 169         LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
 170
 171       SDValue
 172         LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
 173       SDValue
 174         LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
 175       SDValue
 176         LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
 177       SDValue
 178         LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
 179
 180       SDValue
 181         LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 182
 183       SDValue
 184         LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 185
 186       SDValue
 187         LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
 188
 189       EVT
 190         genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
 191
 192       SDValue
 193         LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 194
 195       SDValue
 196         LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 197
 198       SDValue
 199         LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
 200       SDValue
 201         LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 202
 203   }; // AMDILTargetLowering
 204 } // end namespace llvm
 205
 206 #endif    // AMDIL_ISELLOWERING_H_