src/gallium/drivers/radeon/AMDILISelLowering.h

   1 //===-- AMDILISelLowering.h - AMDIL DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that AMDIL uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef AMDIL_ISELLOWERING_H_
  16 #define AMDIL_ISELLOWERING_H_
  17 #include "AMDIL.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21 #include "llvm/Target/TargetLowering.h"
  22
  23 namespace llvm
  24 {
  25   namespace AMDILISD
  26   {
  27     enum
  28     {
  29       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  30       INTTOANY,    // Dummy instruction that takes an int and goes to
  31       // any type converts the SDNode to an int
  32       DP_TO_FP,    // Conversion from 64bit FP to 32bit FP
  33       FP_TO_DP,    // Conversion from 32bit FP to 64bit FP
  34       BITCONV,     // instruction that converts from any type to any type
  35       CMOV,        // 32bit FP Conditional move instruction
  36       CMOVLOG,     // 32bit FP Conditional move logical instruction
  37       SELECT,      // 32bit FP Conditional move logical instruction
  38       SETCC,       // 32bit FP Conditional move logical instruction
  39       ISGN,        // 32bit Int Sign instruction
  40       INEGATE,     // 32bit Int Negation instruction
  41       MAD,         // 32bit Fused Multiply Add instruction
  42       ADD,         // 32/64 bit pseudo instruction
  43       AND,         // 128 bit and instruction
  44       OR,          // 128 bit or instruction
  45       NOT,         // 128 bit not instruction
  46       XOR,         // 128 bit xor instruction
  47       MOVE,        // generic mov instruction
  48       PHIMOVE,     // generic phi-node mov instruction
  49       VBUILD,      // scalar to vector mov instruction
  50       VEXTRACT,    // extract vector components
  51       VINSERT,     // insert vector components
  52       VCONCAT,     // concat a single vector to another vector
  53       UMAD,        // 32bit UInt Fused Multiply Add instruction
  54       CALL,        // Function call based on a single integer
  55       RET,         // Return from a function call
  56       SELECT_CC,   // Select the correct conditional instruction
  57       BRCC,        // Select the correct branch instruction
  58       CMPCC,       // Compare to GPR operands
  59       CMPICC,      // Compare two GPR operands, set icc.
  60       CMPFCC,      // Compare two FP operands, set fcc.
  61       BRICC,       // Branch to dest on icc condition
  62       BRFCC,       // Branch to dest on fcc condition
  63       SELECT_ICC,  // Select between two values using the current ICC
  64       //flags.
  65       SELECT_FCC,  // Select between two values using the current FCC
  66       //flags.
  67       LCREATE,     // Create a 64bit integer from two 32 bit integers
  68       LCOMPHI,     // Get the hi 32 bits from a 64 bit integer
  69       LCOMPLO,     // Get the lo 32 bits from a 64 bit integer
  70       DCREATE,     // Create a 64bit float from two 32 bit integers
  71       DCOMPHI,     // Get the hi 32 bits from a 64 bit float
  72       DCOMPLO,     // Get the lo 32 bits from a 64 bit float
  73       LCREATE2,     // Create a 64bit integer from two 32 bit integers
  74       LCOMPHI2,     // Get the hi 32 bits from a 64 bit integer
  75       LCOMPLO2,     // Get the lo 32 bits from a 64 bit integer
  76       DCREATE2,     // Create a 64bit float from two 32 bit integers
  77       DCOMPHI2,     // Get the hi 32 bits from a 64 bit float
  78       DCOMPLO2,     // Get the lo 32 bits from a 64 bit float
  79       UMUL,        // 32bit unsigned multiplication
  80       IFFB_HI,  // 32bit find first hi bit instruction
  81       IFFB_LO,  // 32bit find first low bit instruction
  82       DIV_INF,      // Divide with infinity returned on zero divisor
  83       SMAX,        // Signed integer max
  84       CMP,
  85       IL_CC_I_GT,
  86       IL_CC_I_LT,
  87       IL_CC_I_GE,
  88       IL_CC_I_LE,
  89       IL_CC_I_EQ,
  90       IL_CC_I_NE,
  91       RET_FLAG,
  92       BRANCH_COND,
  93       LOOP_NZERO,
  94       LOOP_ZERO,
  95       LOOP_CMP,
  96       ADDADDR,
  97       // ATOMIC Operations
  98       // Global Memory
  99       ATOM_G_ADD = ISD::FIRST_TARGET_MEMORY_OPCODE,
 100       ATOM_G_AND,
 101       ATOM_G_CMPXCHG,
 102       ATOM_G_DEC,
 103       ATOM_G_INC,
 104       ATOM_G_MAX,
 105       ATOM_G_UMAX,
 106       ATOM_G_MIN,
 107       ATOM_G_UMIN,
 108       ATOM_G_OR,
 109       ATOM_G_SUB,
 110       ATOM_G_RSUB,
 111       ATOM_G_XCHG,
 112       ATOM_G_XOR,
 113       ATOM_G_ADD_NORET,
 114       ATOM_G_AND_NORET,
 115       ATOM_G_CMPXCHG_NORET,
 116       ATOM_G_DEC_NORET,
 117       ATOM_G_INC_NORET,
 118       ATOM_G_MAX_NORET,
 119       ATOM_G_UMAX_NORET,
 120       ATOM_G_MIN_NORET,
 121       ATOM_G_UMIN_NORET,
 122       ATOM_G_OR_NORET,
 123       ATOM_G_SUB_NORET,
 124       ATOM_G_RSUB_NORET,
 125       ATOM_G_XCHG_NORET,
 126       ATOM_G_XOR_NORET,
 127       // Local Memory
 128       ATOM_L_ADD,
 129       ATOM_L_AND,
 130       ATOM_L_CMPXCHG,
 131       ATOM_L_DEC,
 132       ATOM_L_INC,
 133       ATOM_L_MAX,
 134       ATOM_L_UMAX,
 135       ATOM_L_MIN,
 136       ATOM_L_UMIN,
 137       ATOM_L_OR,
 138       ATOM_L_MSKOR,
 139       ATOM_L_SUB,
 140       ATOM_L_RSUB,
 141       ATOM_L_XCHG,
 142       ATOM_L_XOR,
 143       ATOM_L_ADD_NORET,
 144       ATOM_L_AND_NORET,
 145       ATOM_L_CMPXCHG_NORET,
 146       ATOM_L_DEC_NORET,
 147       ATOM_L_INC_NORET,
 148       ATOM_L_MAX_NORET,
 149       ATOM_L_UMAX_NORET,
 150       ATOM_L_MIN_NORET,
 151       ATOM_L_UMIN_NORET,
 152       ATOM_L_OR_NORET,
 153       ATOM_L_MSKOR_NORET,
 154       ATOM_L_SUB_NORET,
 155       ATOM_L_RSUB_NORET,
 156       ATOM_L_XCHG_NORET,
 157       ATOM_L_XOR_NORET,
 158       // Region Memory
 159       ATOM_R_ADD,
 160       ATOM_R_AND,
 161       ATOM_R_CMPXCHG,
 162       ATOM_R_DEC,
 163       ATOM_R_INC,
 164       ATOM_R_MAX,
 165       ATOM_R_UMAX,
 166       ATOM_R_MIN,
 167       ATOM_R_UMIN,
 168       ATOM_R_OR,
 169       ATOM_R_MSKOR,
 170       ATOM_R_SUB,
 171       ATOM_R_RSUB,
 172       ATOM_R_XCHG,
 173       ATOM_R_XOR,
 174       ATOM_R_ADD_NORET,
 175       ATOM_R_AND_NORET,
 176       ATOM_R_CMPXCHG_NORET,
 177       ATOM_R_DEC_NORET,
 178       ATOM_R_INC_NORET,
 179       ATOM_R_MAX_NORET,
 180       ATOM_R_UMAX_NORET,
 181       ATOM_R_MIN_NORET,
 182       ATOM_R_UMIN_NORET,
 183       ATOM_R_OR_NORET,
 184       ATOM_R_MSKOR_NORET,
 185       ATOM_R_SUB_NORET,
 186       ATOM_R_RSUB_NORET,
 187       ATOM_R_XCHG_NORET,
 188       ATOM_R_XOR_NORET,
 189       // Append buffer
 190       APPEND_ALLOC,
 191       APPEND_ALLOC_NORET,
 192       APPEND_CONSUME,
 193       APPEND_CONSUME_NORET,
 194       // 2D Images
 195       IMAGE2D_READ,
 196       IMAGE2D_WRITE,
 197       IMAGE2D_INFO0,
 198       IMAGE2D_INFO1,
 199       // 3D Images
 200       IMAGE3D_READ,
 201       IMAGE3D_WRITE,
 202       IMAGE3D_INFO0,
 203       IMAGE3D_INFO1,
 204
 205       LAST_ISD_NUMBER
 206     };
 207   } // AMDILISD
 208
 209   class MachineBasicBlock;
 210   class MachineInstr;
 211   class DebugLoc;
 212   class TargetInstrInfo;
 213
 214   class AMDILTargetLowering : public TargetLowering
 215   {
 216     private:
 217       int VarArgsFrameOffset;   // Frame offset to start of varargs area.
 218     public:
 219       AMDILTargetLowering(TargetMachine &TM);
 220
 221       virtual SDValue
 222         LowerOperation(SDValue Op, SelectionDAG &DAG) const;
 223
 224       int
 225         getVarArgsFrameOffset() const;
 226
 227       /// computeMaskedBitsForTargetNode - Determine which of
 228       /// the bits specified
 229       /// in Mask are known to be either zero or one and return them in
 230       /// the
 231       /// KnownZero/KnownOne bitsets.
 232       virtual void
 233         computeMaskedBitsForTargetNode(
 234             const SDValue Op,
 235             APInt &KnownZero,
 236             APInt &KnownOne,
 237             const SelectionDAG &DAG,
 238             unsigned Depth = 0
 239             ) const;
 240
 241       virtual MachineBasicBlock*
 242         EmitInstrWithCustomInserter(
 243             MachineInstr *MI,
 244             MachineBasicBlock *MBB) const;
 245
 246       virtual bool
 247         getTgtMemIntrinsic(IntrinsicInfo &Info,
 248                                   const CallInst &I, unsigned Intrinsic) const;
 249       virtual const char*
 250         getTargetNodeName(
 251             unsigned Opcode
 252             ) const;
 253       // We want to mark f32/f64 floating point values as
 254       // legal
 255       bool
 256         isFPImmLegal(const APFloat &Imm, EVT VT) const;
 257       // We don't want to shrink f64/f32 constants because
 258       // they both take up the same amount of space and
 259       // we don't want to use a f2d instruction.
 260       bool ShouldShrinkFPConstant(EVT VT) const;
 261
 262       /// getFunctionAlignment - Return the Log2 alignment of this
 263       /// function.
 264       virtual unsigned int
 265         getFunctionAlignment(const Function *F) const;
 266
 267     private:
 268       CCAssignFn*
 269         CCAssignFnForNode(unsigned int CC) const;
 270
 271       SDValue LowerCallResult(SDValue Chain,
 272           SDValue InFlag,
 273           CallingConv::ID CallConv,
 274           bool isVarArg,
 275           const SmallVectorImpl<ISD::InputArg> &Ins,
 276           DebugLoc dl,
 277           SelectionDAG &DAG,
 278           SmallVectorImpl<SDValue> &InVals) const;
 279
 280       SDValue LowerMemArgument(SDValue Chain,
 281           CallingConv::ID CallConv,
 282           const SmallVectorImpl<ISD::InputArg> &ArgInfo,
 283           DebugLoc dl, SelectionDAG &DAG,
 284           const CCValAssign &VA,  MachineFrameInfo *MFI,
 285           unsigned i) const;
 286
 287       SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
 288           SDValue Arg,
 289           DebugLoc dl, SelectionDAG &DAG,
 290           const CCValAssign &VA,
 291           ISD::ArgFlagsTy Flags) const;
 292
 293       virtual SDValue
 294         LowerFormalArguments(SDValue Chain,
 295             CallingConv::ID CallConv, bool isVarArg,
 296             const SmallVectorImpl<ISD::InputArg> &Ins,
 297             DebugLoc dl, SelectionDAG &DAG,
 298             SmallVectorImpl<SDValue> &InVals) const;
 299
 300       virtual SDValue
 301         LowerCall(SDValue Chain, SDValue Callee,
 302             CallingConv::ID CallConv, bool isVarArg, bool doesNotRet,
 303             bool &isTailCall,
 304             const SmallVectorImpl<ISD::OutputArg> &Outs,
 305             const SmallVectorImpl<SDValue> &OutVals,
 306             const SmallVectorImpl<ISD::InputArg> &Ins,
 307             DebugLoc dl, SelectionDAG &DAG,
 308             SmallVectorImpl<SDValue> &InVals) const;
 309
 310       virtual SDValue
 311         LowerReturn(SDValue Chain,
 312             CallingConv::ID CallConv, bool isVarArg,
 313             const SmallVectorImpl<ISD::OutputArg> &Outs,
 314             const SmallVectorImpl<SDValue> &OutVals,
 315             DebugLoc dl, SelectionDAG &DAG) const;
 316
 317       //+++--- Function dealing with conversions between floating point and
 318       //integer types ---+++//
 319       SDValue
 320         genCLZu64(SDValue Op, SelectionDAG &DAG) const;
 321       SDValue
 322         genCLZuN(SDValue Op, SelectionDAG &DAG, uint32_t bits) const;
 323       SDValue
 324         genCLZu32(SDValue Op, SelectionDAG &DAG) const;
 325       SDValue
 326         genf64toi32(SDValue Op, SelectionDAG &DAG,
 327             bool includeSign) const;
 328
 329       SDValue
 330         genf64toi64(SDValue Op, SelectionDAG &DAG,
 331             bool includeSign) const;
 332
 333       SDValue
 334         genu32tof64(SDValue Op, EVT dblvt, SelectionDAG &DAG) const;
 335
 336       SDValue
 337         genu64tof64(SDValue Op, EVT dblvt, SelectionDAG &DAG) const;
 338
 339       SDValue
 340         LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 341
 342       SDValue
 343         LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
 344
 345       SDValue
 346         LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 347
 348       SDValue
 349         LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 350
 351       SDValue
 352         LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 353
 354       SDValue
 355         LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG& DAG) const;
 356
 357       SDValue
 358         LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG& DAG) const;
 359
 360       SDValue
 361         LowerINTRINSIC_VOID(SDValue Op, SelectionDAG& DAG) const;
 362
 363       SDValue
 364         LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 365
 366       SDValue
 367         LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 368
 369       SDValue
 370         LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
 371
 372       SDValue
 373         LowerADD(SDValue Op, SelectionDAG &DAG) const;
 374
 375       SDValue
 376         LowerSUB(SDValue Op, SelectionDAG &DAG) const;
 377
 378       SDValue
 379         LowerSREM(SDValue Op, SelectionDAG &DAG) const;
 380       SDValue
 381         LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
 382       SDValue
 383         LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
 384       SDValue
 385         LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
 386       SDValue
 387         LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
 388
 389       SDValue
 390         LowerUREM(SDValue Op, SelectionDAG &DAG) const;
 391       SDValue
 392         LowerUREM8(SDValue Op, SelectionDAG &DAG) const;
 393       SDValue
 394         LowerUREM16(SDValue Op, SelectionDAG &DAG) const;
 395       SDValue
 396         LowerUREM32(SDValue Op, SelectionDAG &DAG) const;
 397       SDValue
 398         LowerUREM64(SDValue Op, SelectionDAG &DAG) const;
 399
 400       SDValue
 401         LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
 402       SDValue
 403         LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
 404       SDValue
 405         LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
 406       SDValue
 407         LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
 408
 409       SDValue
 410         LowerUDIV(SDValue Op, SelectionDAG &DAG) const;
 411       SDValue
 412         LowerUDIV24(SDValue Op, SelectionDAG &DAG) const;
 413       SDValue
 414         LowerUDIV32(SDValue Op, SelectionDAG &DAG) const;
 415       SDValue
 416         LowerUDIV64(SDValue Op, SelectionDAG &DAG) const;
 417
 418       SDValue
 419         LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
 420       SDValue
 421         LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
 422       SDValue
 423         LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
 424
 425       SDValue
 426         LowerMUL(SDValue Op, SelectionDAG &DAG) const;
 427
 428       SDValue
 429         LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 430
 431       SDValue
 432         LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 433
 434       SDValue
 435         LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 436
 437       SDValue
 438         LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
 439
 440       SDValue
 441         LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 442
 443       SDValue
 444         LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
 445
 446       SDValue
 447         LowerAND(SDValue Op, SelectionDAG &DAG) const;
 448
 449       SDValue
 450         LowerOR(SDValue Op, SelectionDAG &DAG) const;
 451
 452       SDValue
 453         LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 454
 455       SDValue
 456         LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 457
 458       SDValue
 459         LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 460
 461       SDValue
 462         LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
 463
 464       EVT
 465         genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
 466
 467       SDValue
 468         LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
 469
 470       SDValue
 471         LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 472
 473       SDValue
 474         LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 475
 476       SDValue
 477         LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
 478       SDValue
 479         LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 480       void
 481         generateCMPInstr(MachineInstr*, MachineBasicBlock*,
 482             const TargetInstrInfo&) const;
 483       MachineOperand
 484         convertToReg(MachineOperand) const;
 485
 486       // private members used by the set of instruction generation
 487       // functions, these are marked mutable as they are cached so
 488       // that they don't have to constantly be looked up when using the
 489       // generateMachineInst/genVReg instructions. This is to simplify
 490       // the code
 491       // and to make it cleaner. The object itself doesn't change as
 492       // only these functions use these three data types.
 493       mutable MachineBasicBlock *mBB;
 494       mutable DebugLoc *mDL;
 495       mutable const TargetInstrInfo *mTII;
 496       mutable MachineBasicBlock::iterator mBBI;
 497       void
 498         setPrivateData(MachineBasicBlock *BB,
 499             MachineBasicBlock::iterator &BBI,
 500             DebugLoc *DL,
 501           const TargetInstrInfo *TII) const;
 502       uint32_t genVReg(uint32_t regType) const;
 503       MachineInstrBuilder
 504         generateMachineInst(uint32_t opcode,
 505           uint32_t dst) const;
 506       MachineInstrBuilder
 507         generateMachineInst(uint32_t opcode,
 508           uint32_t dst, uint32_t src1) const;
 509       MachineInstrBuilder
 510         generateMachineInst(uint32_t opcode,
 511           uint32_t dst, uint32_t src1, uint32_t src2) const;
 512       MachineInstrBuilder
 513         generateMachineInst(uint32_t opcode,
 514           uint32_t dst, uint32_t src1, uint32_t src2,
 515           uint32_t src3) const;
 516       uint32_t
 517         addExtensionInstructions(
 518           uint32_t reg, bool signedShift,
 519           unsigned int simpleVT) const;
 520       void
 521         generateLongRelational(MachineInstr *MI,
 522           unsigned int opCode) const;
 523
 524   }; // AMDILTargetLowering
 525 } // end namespace llvm
 526
 527 #endif    // AMDIL_ISELLOWERING_H_