src/gallium/drivers/radeon/AMDILInstrInfo.h

   1 //===- AMDILInstrInfo.h - AMDIL Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file contains the AMDIL implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef AMDILINSTRUCTIONINFO_H_
  15 #define AMDILINSTRUCTIONINFO_H_
  16
  17 #include "AMDILRegisterInfo.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "AMDGPUGenInstrInfo.inc"
  22
  23 namespace llvm {
  24   // AMDIL - This namespace holds all of the target specific flags that
  25   // instruction info tracks.
  26   //
  27   //class AMDILTargetMachine;
  28 class AMDILInstrInfo : public AMDILGenInstrInfo {
  29 private:
  30   const AMDILRegisterInfo RI;
  31   TargetMachine &TM;
  32   bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
  33                           MachineBasicBlock &MBB) const;
  34   unsigned int getBranchInstr(const MachineOperand &op) const;
  35 public:
  36   explicit AMDILInstrInfo(TargetMachine &tm);
  37
  38   // getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  39   // such, whenever a client has an instance of instruction info, it should
  40   // always be able to get register info as well (through this method).
  41   const AMDILRegisterInfo &getRegisterInfo() const;
  42
  43   bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
  44                              unsigned &DstReg, unsigned &SubIdx) const;
  45
  46   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  47   unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
  48                                      int &FrameIndex) const;
  49   bool hasLoadFromStackSlot(const MachineInstr *MI,
  50                             const MachineMemOperand *&MMO,
  51                             int &FrameIndex) const;
  52   unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  53   unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
  54                                       int &FrameIndex) const;
  55   bool hasStoreFromStackSlot(const MachineInstr *MI,
  56                              const MachineMemOperand *&MMO,
  57                              int &FrameIndex) const;
  58
  59   MachineInstr *
  60   convertToThreeAddress(MachineFunction::iterator &MFI,
  61                         MachineBasicBlock::iterator &MBBI,
  62                         LiveVariables *LV) const;
  63
  64   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  65                      MachineBasicBlock *&FBB,
  66                      SmallVectorImpl<MachineOperand> &Cond,
  67                      bool AllowModify) const;
  68
  69   unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  70
  71   unsigned
  72   InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  73                MachineBasicBlock *FBB,
  74                const SmallVectorImpl<MachineOperand> &Cond,
  75                DebugLoc DL) const;
  76
  77   virtual void copyPhysReg(MachineBasicBlock &MBB,
  78                            MachineBasicBlock::iterator MI, DebugLoc DL,
  79                            unsigned DestReg, unsigned SrcReg,
  80                            bool KillSrc) const = 0;
  81
  82   void storeRegToStackSlot(MachineBasicBlock &MBB,
  83                            MachineBasicBlock::iterator MI,
  84                            unsigned SrcReg, bool isKill, int FrameIndex,
  85                            const TargetRegisterClass *RC,
  86                            const TargetRegisterInfo *TRI) const;
  87   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  88                             MachineBasicBlock::iterator MI,
  89                             unsigned DestReg, int FrameIndex,
  90                             const TargetRegisterClass *RC,
  91                             const TargetRegisterInfo *TRI) const;
  92
  93 protected:
  94   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
  95                                       MachineInstr *MI,
  96                                       const SmallVectorImpl<unsigned> &Ops,
  97                                       int FrameIndex) const;
  98   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
  99                                       MachineInstr *MI,
 100                                       const SmallVectorImpl<unsigned> &Ops,
 101                                       MachineInstr *LoadMI) const;
 102 public:
 103   bool canFoldMemoryOperand(const MachineInstr *MI,
 104                             const SmallVectorImpl<unsigned> &Ops) const;
 105   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
 106                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
 107                            SmallVectorImpl<MachineInstr *> &NewMIs) const;
 108   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
 109                            SmallVectorImpl<SDNode *> &NewNodes) const;
 110   unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
 111                                       bool UnfoldLoad, bool UnfoldStore,
 112                                       unsigned *LoadRegIndex = 0) const;
 113   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
 114                                int64_t Offset1, int64_t Offset2,
 115                                unsigned NumLoads) const;
 116
 117   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 118   void insertNoop(MachineBasicBlock &MBB,
 119                   MachineBasicBlock::iterator MI) const;
 120   bool isPredicated(const MachineInstr *MI) const;
 121   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 122                          const SmallVectorImpl<MachineOperand> &Pred2) const;
 123   bool DefinesPredicate(MachineInstr *MI,
 124                         std::vector<MachineOperand> &Pred) const;
 125   bool isPredicable(MachineInstr *MI) const;
 126   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
 127
 128   // Helper functions that check the opcode for status information
 129   bool isLoadInst(llvm::MachineInstr *MI) const;
 130   bool isExtLoadInst(llvm::MachineInstr *MI) const;
 131   bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
 132   bool isSExtLoadInst(llvm::MachineInstr *MI) const;
 133   bool isZExtLoadInst(llvm::MachineInstr *MI) const;
 134   bool isAExtLoadInst(llvm::MachineInstr *MI) const;
 135   bool isStoreInst(llvm::MachineInstr *MI) const;
 136   bool isTruncStoreInst(llvm::MachineInstr *MI) const;
 137   bool isAtomicInst(llvm::MachineInstr *MI) const;
 138   bool isVolatileInst(llvm::MachineInstr *MI) const;
 139   bool isGlobalInst(llvm::MachineInstr *MI) const;
 140   bool isPrivateInst(llvm::MachineInstr *MI) const;
 141   bool isConstantInst(llvm::MachineInstr *MI) const;
 142   bool isRegionInst(llvm::MachineInstr *MI) const;
 143   bool isLocalInst(llvm::MachineInstr *MI) const;
 144   bool isImageInst(llvm::MachineInstr *MI) const;
 145   bool isAppendInst(llvm::MachineInstr *MI) const;
 146   bool isRegionAtomic(llvm::MachineInstr *MI) const;
 147   bool isLocalAtomic(llvm::MachineInstr *MI) const;
 148   bool isGlobalAtomic(llvm::MachineInstr *MI) const;
 149   bool isArenaAtomic(llvm::MachineInstr *MI) const;
 150
 151   virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
 152                                         int64_t Imm) const = 0;
 153
 154   virtual unsigned getIEQOpcode() const = 0;
 155
 156   virtual bool isMov(unsigned Opcode) const = 0;
 157 };
 158
 159 }
 160
 161 #endif // AMDILINSTRINFO_H_