src/gallium/drivers/radeon/AMDILInstrInfo.h

   1 //===- AMDILInstrInfo.h - AMDIL Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file contains the AMDIL implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef AMDILINSTRUCTIONINFO_H_
  15 #define AMDILINSTRUCTIONINFO_H_
  16
  17 #include "AMDILRegisterInfo.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "AMDILGenInstrInfo.inc"
  22
  23 namespace llvm {
  24   // AMDIL - This namespace holds all of the target specific flags that
  25   // instruction info tracks.
  26   //
  27   //class AMDILTargetMachine;
  28 class AMDILInstrInfo : public AMDILGenInstrInfo {
  29 private:
  30   const AMDILRegisterInfo RI;
  31   AMDILTargetMachine &TM;
  32   bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
  33                           MachineBasicBlock &MBB) const;
  34   unsigned int getBranchInstr(const MachineOperand &op) const;
  35 public:
  36   explicit AMDILInstrInfo(AMDILTargetMachine &tm);
  37
  38   // getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  39   // such, whenever a client has an instance of instruction info, it should
  40   // always be able to get register info as well (through this method).
  41   const AMDILRegisterInfo &getRegisterInfo() const;
  42
  43   // Return true if the instruction is a register to register move and leave the
  44   // source and dest operands in the passed parameters.
  45   bool isMoveInstr(const MachineInstr &MI, unsigned int &SrcReg,
  46                    unsigned int &DstReg, unsigned int &SrcSubIdx,
  47                    unsigned int &DstSubIdx) const;
  48
  49   bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
  50                              unsigned &DstReg, unsigned &SubIdx) const;
  51
  52   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  53   unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
  54                                      int &FrameIndex) const;
  55   bool hasLoadFromStackSlot(const MachineInstr *MI,
  56                             const MachineMemOperand *&MMO,
  57                             int &FrameIndex) const;
  58   unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  59   unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
  60                                       int &FrameIndex) const;
  61   bool hasStoreFromStackSlot(const MachineInstr *MI,
  62                              const MachineMemOperand *&MMO,
  63                              int &FrameIndex) const;
  64
  65
  66 #if 0
  67   void reMaterialize(MachineBasicBlock &MBB,
  68                      MachineBasicBlock::iterator MI,
  69                      unsigned DestReg, unsigned SubIdx,
  70                      const MachineInstr *Orig,
  71                      const TargetRegisterInfo *TRI) const;
  72   MachineInstr *duplicate(MachineInstr *Orig,
  73                           MachineFunction &MF) const;
  74 #endif
  75   MachineInstr *
  76   convertToThreeAddress(MachineFunction::iterator &MFI,
  77                         MachineBasicBlock::iterator &MBBI,
  78                         LiveVariables *LV) const;
  79 #if 0
  80   MachineInstr *commuteInstruction(MachineInstr *MI,
  81                                    bool NewMI = false) const;
  82   bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
  83                              unsigned &SrcOpIdx2) const;
  84   bool produceSameValue(const MachineInstr *MI0,
  85                         const MachineInstr *MI1) const;
  86
  87 #endif
  88
  89   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  90                      MachineBasicBlock *&FBB,
  91                      SmallVectorImpl<MachineOperand> &Cond,
  92                      bool AllowModify) const;
  93
  94   unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  95
  96   unsigned
  97   InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  98                MachineBasicBlock *FBB,
  99                const SmallVectorImpl<MachineOperand> &Cond,
 100                DebugLoc DL) const;
 101
 102   bool copyRegToReg(MachineBasicBlock &MBB,
 103                     MachineBasicBlock::iterator I,
 104                     unsigned DestReg, unsigned SrcReg,
 105                     const TargetRegisterClass *DestRC,
 106                     const TargetRegisterClass *SrcRC,
 107                     DebugLoc DL) const;
 108   virtual void copyPhysReg(MachineBasicBlock &MBB,
 109                            MachineBasicBlock::iterator MI, DebugLoc DL,
 110                            unsigned DestReg, unsigned SrcReg,
 111                            bool KillSrc) const;
 112
 113   void storeRegToStackSlot(MachineBasicBlock &MBB,
 114                            MachineBasicBlock::iterator MI,
 115                            unsigned SrcReg, bool isKill, int FrameIndex,
 116                            const TargetRegisterClass *RC,
 117                            const TargetRegisterInfo *TRI) const;
 118   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 119                             MachineBasicBlock::iterator MI,
 120                             unsigned DestReg, int FrameIndex,
 121                             const TargetRegisterClass *RC,
 122                             const TargetRegisterInfo *TRI) const;
 123
 124 protected:
 125   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
 126                                       MachineInstr *MI,
 127                                       const SmallVectorImpl<unsigned> &Ops,
 128                                       int FrameIndex) const;
 129   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
 130                                       MachineInstr *MI,
 131                                       const SmallVectorImpl<unsigned> &Ops,
 132                                       MachineInstr *LoadMI) const;
 133 public:
 134   bool canFoldMemoryOperand(const MachineInstr *MI,
 135                             const SmallVectorImpl<unsigned> &Ops) const;
 136   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
 137                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
 138                            SmallVectorImpl<MachineInstr *> &NewMIs) const;
 139   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
 140                            SmallVectorImpl<SDNode *> &NewNodes) const;
 141   unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
 142                                       bool UnfoldLoad, bool UnfoldStore,
 143                                       unsigned *LoadRegIndex = 0) const;
 144   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
 145                                int64_t &Offset1, int64_t &Offset2) const;
 146   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
 147                                int64_t Offset1, int64_t Offset2,
 148                                unsigned NumLoads) const;
 149
 150   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 151   void insertNoop(MachineBasicBlock &MBB,
 152                   MachineBasicBlock::iterator MI) const;
 153   bool isPredicated(const MachineInstr *MI) const;
 154 #if 0
 155   bool isUnpredicatedTerminator(const MachineInstr *MI) const;
 156   bool PredicateInstruction(MachineInstr *MI,
 157                             const SmallVectorImpl<MachineOperand> &Pred) const;
 158 #endif
 159   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 160                          const SmallVectorImpl<MachineOperand> &Pred2) const;
 161   bool DefinesPredicate(MachineInstr *MI,
 162                         std::vector<MachineOperand> &Pred) const;
 163   bool isPredicable(MachineInstr *MI) const;
 164   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
 165   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 166 #if 0
 167   unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
 168   unsigned getInlineAsmLength(const char *Str,
 169                               const MCAsmInfo &MAI) const;
 170 #endif
 171   };
 172
 173 }
 174
 175 #endif // AMDILINSTRINFO_H_