radeon/llvm: Move lowering of SETCC node to R600ISelLowering
[mesa.git] / src / gallium / drivers / radeon / AMDILInstructions.td
1 //===-- AMDILInstructions.td - AMDIL Instruction definitions --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //==-----------------------------------------------------------------------===//
9
10 let Predicates = [Has32BitPtr] in {
11 let isCodeGenOnly=1 in {
12 //===----------------------------------------------------------------------===//
13 // Store Memory Operations
14 //===----------------------------------------------------------------------===//
15 defm GLOBALTRUNCSTORE : GTRUNCSTORE<"!global trunc store">;
16 defm LOCALTRUNCSTORE : LTRUNCSTORE<"!local trunc store">;
17 defm LOCALSTORE : STORE<"!local store" , local_store>;
18 defm PRIVATETRUNCSTORE : PTRUNCSTORE<"!private trunc store">;
19 defm PRIVATESTORE : STORE<"!private store" , private_store>;
20 defm REGIONTRUNCSTORE : RTRUNCSTORE<"!region trunc store">;
21 defm REGIONSTORE : STORE<"!region hw store" , region_store>;
22
23
24 //===---------------------------------------------------------------------===//
25 // Load Memory Operations
26 //===---------------------------------------------------------------------===//
27 defm GLOBALZEXTLOAD : LOAD<"!global zext load" , global_zext_load>;
28 defm GLOBALSEXTLOAD : LOAD<"!global sext load" , global_sext_load>;
29 defm GLOBALAEXTLOAD : LOAD<"!global aext load" , global_aext_load>;
30 defm PRIVATELOAD : LOAD<"!private load" , private_load>;
31 defm PRIVATEZEXTLOAD : LOAD<"!private zext load" , private_zext_load>;
32 defm PRIVATESEXTLOAD : LOAD<"!private sext load" , private_sext_load>;
33 defm PRIVATEAEXTLOAD : LOAD<"!private aext load" , private_aext_load>;
34 defm CPOOLLOAD : LOAD<"!constant pool load" , cp_load>;
35 defm CPOOLZEXTLOAD : LOAD<"!constant pool zext load", cp_zext_load>;
36 defm CPOOLSEXTLOAD : LOAD<"!constant pool sext load", cp_sext_load>;
37 defm CPOOLAEXTLOAD : LOAD<"!constant aext pool load", cp_aext_load>;
38 defm CONSTANTLOAD : LOAD<"!constant load" , constant_load>;
39 defm CONSTANTZEXTLOAD : LOAD<"!constant zext load" , constant_zext_load>;
40 defm CONSTANTSEXTLOAD : LOAD<"!constant sext load" , constant_sext_load>;
41 defm CONSTANTAEXTLOAD : LOAD<"!constant aext load" , constant_aext_load>;
42 defm LOCALLOAD : LOAD<"!local load" , local_load>;
43 defm LOCALZEXTLOAD : LOAD<"!local zext load" , local_zext_load>;
44 defm LOCALSEXTLOAD : LOAD<"!local sext load" , local_sext_load>;
45 defm LOCALAEXTLOAD : LOAD<"!local aext load" , local_aext_load>;
46 defm REGIONLOAD : LOAD<"!region load" , region_load>;
47 defm REGIONZEXTLOAD : LOAD<"!region zext load" , region_zext_load>;
48 defm REGIONSEXTLOAD : LOAD<"!region sext load" , region_sext_load>;
49 defm REGIONAEXTLOAD : LOAD<"!region aext load" , region_aext_load>;
50 }
51 }
52
53 //===---------------------------------------------------------------------===//
54 // Custom Inserter for Branches and returns, this eventually will be a
55 // seperate pass
56 //===---------------------------------------------------------------------===//
57 let isTerminator = 1 in {
58 def BRANCH : ILFormat<IL_PSEUDO_INST, (outs), (ins brtarget:$target),
59 "; Pseudo unconditional branch instruction",
60 [(br bb:$target)]>;
61 defm BRANCH_COND : BranchConditional<IL_brcond>;
62 }
63 //===---------------------------------------------------------------------===//
64 // return instructions
65 //===---------------------------------------------------------------------===//
66 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
67 def RETURN : ILFormat<IL_OP_RET,(outs), (ins variable_ops),
68 IL_OP_RET.Text, [(IL_retflag)]>;
69 }
70
71 //===---------------------------------------------------------------------===//
72 // Handle a function call
73 //===---------------------------------------------------------------------===//
74 let isCall = 1,
75 Defs = [
76 R1, R2, R3, R4, R5, R6, R7, R8, R9, R10
77 ]
78 ,
79 Uses = [
80 R11, R12, R13, R14, R15, R16, R17, R18, R19, R20
81 ]
82 in {
83 def CALL : UnaryOpNoRet<IL_OP_CALL, (outs),
84 (ins calltarget:$dst, variable_ops),
85 !strconcat(IL_OP_CALL.Text, " $dst"), []>;
86 }
87
88
89 //===---------------------------------------------------------------------===//
90 // Flow and Program control Instructions
91 //===---------------------------------------------------------------------===//
92 let isTerminator=1 in {
93 def SWITCH : ILFormat<IL_OP_SWITCH, (outs), (ins GPRI32:$src),
94 !strconcat(IL_OP_SWITCH.Text, " $src"), []>;
95 def CASE : ILFormat<IL_OP_CASE, (outs), (ins GPRI32:$src),
96 !strconcat(IL_OP_CASE.Text, " $src"), []>;
97 def BREAK : ILFormat<IL_OP_BREAK, (outs), (ins),
98 IL_OP_BREAK.Text, []>;
99 def CONTINUE : ILFormat<IL_OP_CONTINUE, (outs), (ins),
100 IL_OP_CONTINUE.Text, []>;
101 def DEFAULT : ILFormat<IL_OP_DEFAULT, (outs), (ins),
102 IL_OP_DEFAULT.Text, []>;
103 def ELSE : ILFormat<IL_OP_ELSE, (outs), (ins),
104 IL_OP_ELSE.Text, []>;
105 def ENDSWITCH : ILFormat<IL_OP_ENDSWITCH, (outs), (ins),
106 IL_OP_ENDSWITCH.Text, []>;
107 def ENDMAIN : ILFormat<IL_OP_ENDMAIN, (outs), (ins),
108 IL_OP_ENDMAIN.Text, []>;
109 def END : ILFormat<IL_OP_END, (outs), (ins),
110 IL_OP_END.Text, []>;
111 def ENDFUNC : ILFormat<IL_OP_ENDFUNC, (outs), (ins),
112 IL_OP_ENDFUNC.Text, []>;
113 def ENDIF : ILFormat<IL_OP_ENDIF, (outs), (ins),
114 IL_OP_ENDIF.Text, []>;
115 def WHILELOOP : ILFormat<IL_OP_WHILE, (outs), (ins),
116 IL_OP_WHILE.Text, []>;
117 def ENDLOOP : ILFormat<IL_OP_ENDLOOP, (outs), (ins),
118 IL_OP_ENDLOOP.Text, []>;
119 def FUNC : ILFormat<IL_OP_FUNC, (outs), (ins),
120 IL_OP_FUNC.Text, []>;
121 def RETDYN : ILFormat<IL_OP_RET_DYN, (outs), (ins),
122 IL_OP_RET_DYN.Text, []>;
123 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
124 defm IF_LOGICALNZ : BranchInstr<IL_OP_IF_LOGICALNZ>;
125 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
126 defm IF_LOGICALZ : BranchInstr<IL_OP_IF_LOGICALZ>;
127 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
128 defm BREAK_LOGICALNZ : BranchInstr<IL_OP_BREAK_LOGICALNZ>;
129 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
130 defm BREAK_LOGICALZ : BranchInstr<IL_OP_BREAK_LOGICALZ>;
131 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
132 defm CONTINUE_LOGICALNZ : BranchInstr<IL_OP_CONTINUE_LOGICALNZ>;
133 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
134 defm CONTINUE_LOGICALZ : BranchInstr<IL_OP_CONTINUE_LOGICALZ>;
135 defm IFC : BranchInstr2<IL_OP_IFC>;
136 defm BREAKC : BranchInstr2<IL_OP_BREAKC>;
137 defm CONTINUEC : BranchInstr2<IL_OP_CONTINUEC>;
138 }
139 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
140 def TRAP : ILFormat<IL_OP_NOP, (outs), (ins),
141 IL_OP_NOP.Text, [(trap)]>;
142 }
143