src/gallium/drivers/radeon/AMDILPointerManager.h

   1 //===-------- AMDILPointerManager.h - Manage Pointers for HW ------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 // The AMDIL Pointer Manager is a class that does all the checking for
  10 // different pointer characteristics. Pointers have attributes that need
  11 // to be attached to them in order to correctly codegen them efficiently.
  12 // This class will analyze the pointers of a function and then traverse the uses
  13 // of the pointers and determine if a pointer can be cached, should belong in
  14 // the arena, and what UAV it should belong to. There are seperate classes for
  15 // each unique generation of devices. This pass only works in SSA form.
  16 //===----------------------------------------------------------------------===//
  17 #ifndef _AMDIL_POINTER_MANAGER_H_
  18 #define _AMDIL_POINTER_MANAGER_H_
  19 #undef DEBUG_TYPE
  20 #undef DEBUGME
  21 #define DEBUG_TYPE "PointerManager"
  22 #if !defined(NDEBUG)
  23 #define DEBUGME (DebugFlag && isCurrentDebugType(DEBUG_TYPE))
  24 #else
  25 #define DEBUGME (false)
  26 #endif
  27 #include "AMDIL.h"
  28 #include "AMDILUtilityFunctions.h"
  29 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
  30 #include "llvm/CodeGen/MachineFunctionPass.h"
  31 #include "llvm/CodeGen/MachineInstr.h"
  32 #include "llvm/CodeGen/MachineMemOperand.h"
  33 #include "llvm/CodeGen/Passes.h"
  34 #include "llvm/Support/Compiler.h"
  35 #include "llvm/Support/Debug.h"
  36 #include "llvm/Target/TargetMachine.h"
  37
  38 #include <list>
  39 #include <map>
  40 #include <queue>
  41 #include <set>
  42
  43 namespace llvm {
  44   class Value;
  45   class MachineBasicBlock;
  46   // Typedefing the multiple different set types to that it is
  47   // easier to read what each set is supposed to handle. This
  48   // also allows it easier to track which set goes to which
  49   // argument in a function call.
  50   typedef std::set<const Value*> PtrSet;
  51
  52   // A Byte set is the set of all base pointers that must
  53   // be allocated to the arena path.
  54   typedef PtrSet ByteSet;
  55
  56   // A Raw set is the set of all base pointers that can be
  57   // allocated to the raw path.
  58   typedef PtrSet RawSet;
  59
  60   // A cacheable set is the set of all base pointers that
  61   // are deamed cacheable based on annotations or
  62   // compiler options.
  63   typedef PtrSet CacheableSet;
  64
  65   // A conflict set is a set of all base pointers whose
  66   // use/def chains conflict with another base pointer.
  67   typedef PtrSet ConflictSet;
  68
  69   // An image set is a set of all read/write only image pointers.
  70   typedef PtrSet ImageSet;
  71
  72   // An append set is a set of atomic counter base pointers
  73   typedef std::vector<const Value*> AppendSet;
  74
  75   // A ConstantSet is a set of constant pool instructions
  76   typedef std::set<MachineInstr*> CPoolSet;
  77
  78   // A CacheableInstSet set is a set of instructions that are cachable
  79   // even if the pointer is not generally cacheable.
  80   typedef std::set<MachineInstr*> CacheableInstrSet;
  81
  82   // A pair that maps a virtual register to the equivalent base
  83   // pointer value that it was derived from.
  84   typedef std::pair<unsigned, const Value*> RegValPair;
  85
  86   // A map that maps between the base pointe rvalue and an array
  87   // of instructions that are part of the pointer chain. A pointer
  88   // chain is a recursive def/use chain of all instructions that don't
  89   // store data to memory unless the pointer is the data being stored.
  90   typedef std::map<const Value*, std::vector<MachineInstr*> > PtrIMap;
  91
  92   // A map that holds a set of all base pointers that are used in a machine
  93   // instruction. This helps to detect when conflict pointers are found
  94   // such as when pointer subtraction occurs.
  95   typedef std::map<MachineInstr*, PtrSet> InstPMap;
  96
  97   // A map that holds the frame index to RegValPair so that writes of
  98   // pointers to the stack can be tracked.
  99   typedef std::map<unsigned, RegValPair > FIPMap;
 100
 101   // A small vector impl that holds all of the register to base pointer
 102   // mappings for a given function.
 103   typedef std::map<unsigned, RegValPair> RVPVec;
 104
 105
 106
 107   // The default pointer manager. This handles pointer
 108   // resource allocation for default ID's only.
 109   // There is no special processing.
 110   class AMDILPointerManager : public MachineFunctionPass
 111   {
 112     public:
 113       AMDILPointerManager(
 114           TargetMachine &tm
 115           AMDIL_OPT_LEVEL_DECL);
 116       virtual ~AMDILPointerManager();
 117       virtual const char*
 118         getPassName() const;
 119       virtual bool
 120         runOnMachineFunction(MachineFunction &F);
 121       virtual void
 122         getAnalysisUsage(AnalysisUsage &AU) const;
 123       static char ID;
 124     protected:
 125       bool mDebug;
 126     private:
 127       TargetMachine &TM;
 128   }; // class AMDILPointerManager
 129
 130   // The pointer manager for Evergreen and Northern Island
 131   // devices. This pointer manager allocates and trackes
 132   // cached memory, arena resources, raw resources and
 133   // whether multi-uav is utilized or not.
 134   class AMDILEGPointerManager : public AMDILPointerManager
 135   {
 136     public:
 137       AMDILEGPointerManager(
 138           TargetMachine &tm
 139           AMDIL_OPT_LEVEL_DECL);
 140       virtual ~AMDILEGPointerManager();
 141       virtual const char*
 142         getPassName() const;
 143       virtual bool
 144         runOnMachineFunction(MachineFunction &F);
 145     private:
 146       TargetMachine &TM;
 147   }; // class AMDILEGPointerManager
 148
 149   // Information related to the cacheability of instructions in a basic block.
 150   // This is used during the parse phase of the pointer algorithm to track
 151   // the reachability of stores within a basic block.
 152   class BlockCacheableInfo {
 153     public:
 154       BlockCacheableInfo() :
 155         mStoreReachesTop(false),
 156         mStoreReachesExit(false),
 157         mCacheableSet()
 158     {};
 159
 160       bool storeReachesTop() const  { return mStoreReachesTop; }
 161       bool storeReachesExit() const { return mStoreReachesExit; }
 162       CacheableInstrSet::const_iterator
 163         cacheableBegin() const { return mCacheableSet.begin(); }
 164       CacheableInstrSet::const_iterator
 165         cacheableEnd()   const { return mCacheableSet.end(); }
 166
 167       // mark the block as having a global store that reaches it. This
 168       // will also set the store reaches exit flag, and clear the list
 169       // of loads (since they are now reachable by a store.)
 170       bool setReachesTop() {
 171         bool changedExit = !mStoreReachesExit;
 172
 173         if (!mStoreReachesTop)
 174           mCacheableSet.clear();
 175
 176         mStoreReachesTop = true;
 177         mStoreReachesExit = true;
 178         return changedExit;
 179       }
 180
 181       // Mark the block as having a store that reaches the exit of the
 182       // block.
 183       void setReachesExit() {
 184         mStoreReachesExit = true;
 185       }
 186
 187       // If the top or the exit of the block are not marked as reachable
 188       // by a store, add the load to the list of cacheable loads.
 189       void addPossiblyCacheableInst(const TargetMachine * tm, MachineInstr *load) {
 190         // By definition, if store reaches top, then store reaches exit.
 191         // So, we only test for exit here.
 192         // If we have a volatile load we cannot cache it.
 193         if (mStoreReachesExit || isVolatileInst(tm->getInstrInfo(), load)) {
 194           return;
 195         }
 196
 197         mCacheableSet.insert(load);
 198       }
 199
 200     private:
 201       bool mStoreReachesTop; // Does a global store reach the top of this block?
 202       bool mStoreReachesExit;// Does a global store reach the exit of this block?
 203       CacheableInstrSet mCacheableSet; // The set of loads in the block not
 204       // reachable by a global store.
 205   };
 206   // Map from MachineBasicBlock to it's cacheable load info.
 207   typedef std::map<MachineBasicBlock*, BlockCacheableInfo> MBBCacheableMap;
 208 } // end llvm namespace
 209 #endif // _AMDIL_POINTER_MANAGER_H_