src/gallium/drivers/radeon/AMDILRegisterInfo.h

   1 //===- AMDILRegisterInfo.h - AMDIL Register Information Impl ----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 // This file contains the AMDIL implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef AMDILREGISTERINFO_H_
  15 #define AMDILREGISTERINFO_H_
  16
  17 #include "llvm/Target/TargetRegisterInfo.h"
  18
  19 #define GET_REGINFO_HEADER
  20 #include "AMDGPUGenRegisterInfo.inc"
  21 // See header file for explanation
  22
  23 namespace llvm
  24 {
  25
  26   class TargetInstrInfo;
  27   class Type;
  28
  29   /// DWARFFlavour - Flavour of dwarf regnumbers
  30   ///
  31   namespace DWARFFlavour {
  32     enum {
  33       AMDIL_Generic = 0
  34     };
  35   }
  36
  37   struct AMDILRegisterInfo : public AMDILGenRegisterInfo
  38   {
  39     TargetMachine &TM;
  40     const TargetInstrInfo &TII;
  41
  42     AMDILRegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
  43     /// Code Generation virtual methods...
  44     const uint16_t * getCalleeSavedRegs(const MachineFunction *MF = 0) const;
  45
  46     const TargetRegisterClass* const*
  47       getCalleeSavedRegClasses(
  48           const MachineFunction *MF = 0) const;
  49
  50     BitVector
  51       getReservedRegs(const MachineFunction &MF) const;
  52     BitVector
  53       getAllocatableSet(const MachineFunction &MF,
  54           const TargetRegisterClass *RC) const;
  55
  56     void
  57       eliminateCallFramePseudoInstr(
  58           MachineFunction &MF,
  59           MachineBasicBlock &MBB,
  60           MachineBasicBlock::iterator I) const;
  61     void
  62       eliminateFrameIndex(MachineBasicBlock::iterator II,
  63           int SPAdj, RegScavenger *RS = NULL) const;
  64
  65     void
  66       processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
  67
  68     // Debug information queries.
  69     unsigned int
  70       getRARegister() const;
  71
  72     unsigned int
  73       getFrameRegister(const MachineFunction &MF) const;
  74
  75     // Exception handling queries.
  76     unsigned int
  77       getEHExceptionRegister() const;
  78     unsigned int
  79       getEHHandlerRegister() const;
  80
  81     int64_t
  82       getStackSize() const;
  83
  84     virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT)
  85                                                                       const {
  86       return AMDGPU::GPRI32RegisterClass;
  87     }
  88     private:
  89     mutable int64_t baseOffset;
  90     mutable int64_t nextFuncOffset;
  91   };
  92
  93 } // end namespace llvm
  94
  95 #endif // AMDILREGISTERINFO_H_