src/gallium/drivers/radeon/AMDILTargetMachine.cpp

   1 //===-- AMDILTargetMachine.cpp - Define TargetMachine for AMDIL -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "AMDILTargetMachine.h"
  13 #include "AMDGPUTargetMachine.h"
  14 #include "AMDILDevices.h"
  15 #include "AMDILFrameLowering.h"
  16 #include "llvm/ADT/OwningPtr.h"
  17 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
  18 #include "llvm/CodeGen/MachineModuleInfo.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/SchedulerRegistry.h"
  21 #include "llvm/MC/MCAsmInfo.h"
  22 #include "llvm/MC/MCContext.h"
  23 #include "llvm/MC/MCStreamer.h"
  24 #include "llvm/Pass.h"
  25 #include "llvm/PassManager.h"
  26 #include "llvm/Support/FormattedStream.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28 #include "llvm/Target/TargetData.h"
  29 #include "llvm/Transforms/Scalar.h"
  30
  31 using namespace llvm;
  32
  33 extern "C" void LLVMInitializeAMDILTarget() {
  34   // Register the target
  35   RegisterTargetMachine<AMDILTargetMachine> X(TheAMDILTarget);
  36   RegisterTargetMachine<AMDGPUTargetMachine> Y(TheAMDGPUTarget);
  37 }
  38
  39 /// AMDILTargetMachine ctor -
  40 ///
  41 AMDILTargetMachine::AMDILTargetMachine(const Target &T,
  42     StringRef TT, StringRef CPU, StringRef FS,
  43     TargetOptions Options,
  44     Reloc::Model RM, CodeModel::Model CM,
  45     CodeGenOpt::Level OL
  46 )
  47 :
  48   LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
  49   Subtarget(TT, CPU, FS),
  50   DataLayout(Subtarget.getDataLayout()),
  51   FrameLowering(TargetFrameLowering::StackGrowsUp,
  52       Subtarget.device()->getStackAlignment(), 0),
  53   InstrInfo(*this), //JITInfo(*this),
  54   TLInfo(*this),
  55   IntrinsicInfo(this),
  56   ELFWriterInfo(false, true)
  57 {
  58   setAsmVerbosityDefault(true);
  59   setMCUseLoc(false);
  60 }
  61
  62 AMDILTargetLowering*
  63 AMDILTargetMachine::getTargetLowering() const
  64 {
  65   return const_cast<AMDILTargetLowering*>(&TLInfo);
  66 }
  67
  68 const AMDILInstrInfo*
  69 AMDILTargetMachine::getInstrInfo() const
  70 {
  71   return &InstrInfo;
  72 }
  73 const AMDILFrameLowering*
  74 AMDILTargetMachine::getFrameLowering() const
  75 {
  76   return &FrameLowering;
  77 }
  78
  79 const AMDILSubtarget*
  80 AMDILTargetMachine::getSubtargetImpl() const
  81 {
  82   return &Subtarget;
  83 }
  84
  85 const AMDILRegisterInfo*
  86 AMDILTargetMachine::getRegisterInfo() const
  87 {
  88   return &InstrInfo.getRegisterInfo();
  89 }
  90
  91 const TargetData*
  92 AMDILTargetMachine::getTargetData() const
  93 {
  94   return &DataLayout;
  95 }
  96
  97 const AMDILELFWriterInfo*
  98 AMDILTargetMachine::getELFWriterInfo() const
  99 {
 100   return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
 101 }
 102
 103 const AMDILIntrinsicInfo*
 104 AMDILTargetMachine::getIntrinsicInfo() const
 105 {
 106   return &IntrinsicInfo;
 107 }
 108
 109   void
 110 AMDILTargetMachine::dump(llvm::raw_ostream &O)
 111 {
 112   if (!mDebugMode) {
 113     return;
 114   }
 115   O << ";AMDIL Target Machine State Dump: \n";
 116 }
 117
 118   void
 119 AMDILTargetMachine::setDebug(bool debugMode)
 120 {
 121   mDebugMode = debugMode;
 122 }
 123
 124 bool
 125 AMDILTargetMachine::getDebug() const
 126 {
 127   return mDebugMode;
 128 }
 129
 130 namespace {
 131 class AMDILPassConfig : public TargetPassConfig {
 132
 133 public:
 134   AMDILPassConfig(AMDILTargetMachine *TM, PassManagerBase &PM)
 135     : TargetPassConfig(TM, PM) {}
 136
 137   AMDILTargetMachine &getAMDILTargetMachine() const {
 138     return getTM<AMDILTargetMachine>();
 139   }
 140
 141   virtual bool addPreISel();
 142   virtual bool addInstSelector();
 143   virtual bool addPreRegAlloc();
 144   virtual bool addPostRegAlloc();
 145   virtual bool addPreEmitPass();
 146 };
 147 } // End of anonymous namespace
 148
 149 TargetPassConfig *AMDILTargetMachine::createPassConfig(PassManagerBase &PM) {
 150   return new AMDILPassConfig(this, PM);
 151 }
 152
 153 bool AMDILPassConfig::addPreISel()
 154 {
 155   return false;
 156 }
 157
 158 bool AMDILPassConfig::addInstSelector()
 159 {
 160   PM.add(createAMDILBarrierDetect(*TM));
 161   PM.add(createAMDILPrintfConvert(*TM));
 162   PM.add(createAMDILInlinePass(*TM));
 163   PM.add(createAMDILPeepholeOpt(*TM));
 164   PM.add(createAMDILISelDag(getAMDILTargetMachine()));
 165   return false;
 166 }
 167
 168 bool AMDILPassConfig::addPreRegAlloc()
 169 {
 170   // If debugging, reduce code motion. Use less aggressive pre-RA scheduler
 171   if (TM->getOptLevel() == CodeGenOpt::None) {
 172     llvm::RegisterScheduler::setDefault(&llvm::createSourceListDAGScheduler);
 173   }
 174
 175   PM.add(createAMDILMachinePeephole(*TM));
 176   return false;
 177 }
 178
 179 bool AMDILPassConfig::addPostRegAlloc() {
 180   return false;  // -print-machineinstr should print after this.
 181 }
 182
 183 /// addPreEmitPass - This pass may be implemented by targets that want to run
 184 /// passes immediately before machine code is emitted.  This should return
 185 /// true if -print-machineinstrs should print out the code after the passes.
 186 bool AMDILPassConfig::addPreEmitPass()
 187 {
 188   PM.add(createAMDILCFGPreparationPass(*TM));
 189   PM.add(createAMDILCFGStructurizerPass(*TM));
 190   PM.add(createAMDILLiteralManager(*TM));
 191   PM.add(createAMDILIOExpansion(*TM));
 192   return true;
 193 }
 194