radeon/llvm: Move lowering of SETCC node to R600ISelLowering
[mesa.git] / src / gallium / drivers / radeon / AMDILVersion.td
1 //===-- AMDILVersion.td - Barrier Instruction/Intrinsic definitions------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===--------------------------------------------------------------------===//
9 // Intrinsic operation support
10 //===--------------------------------------------------------------------===//
11 let TargetPrefix = "AMDIL", isTarget = 1 in {
12 def int_AMDIL_barrier : GCCBuiltin<"barrier">,
13 BinaryIntNoRetInt;
14 def int_AMDIL_barrier_global : GCCBuiltin<"barrierGlobal">,
15 BinaryIntNoRetInt;
16 def int_AMDIL_barrier_local : GCCBuiltin<"barrierLocal">,
17 BinaryIntNoRetInt;
18 def int_AMDIL_barrier_region : GCCBuiltin<"barrierRegion">,
19 BinaryIntNoRetInt;
20 def int_AMDIL_get_region_id : GCCBuiltin<"__amdil_get_region_id_int">,
21 Intrinsic<[llvm_v4i32_ty], [], []>;
22 def int_AMDIL_get_region_local_id : GCCBuiltin<"__amdil_get_region_local_id_int">,
23 Intrinsic<[llvm_v4i32_ty], [], []>;
24 def int_AMDIL_get_num_regions : GCCBuiltin<"__amdil_get_num_regions_int">,
25 Intrinsic<[llvm_v4i32_ty], [], []>;
26 def int_AMDIL_get_region_size : GCCBuiltin<"__amdil_get_region_size_int">,
27 Intrinsic<[llvm_v4i32_ty], [], []>;
28 }
29
30 let isCall=1, isNotDuplicable=1 in {
31 let Predicates=[hasRegionAS] in {
32 def BARRIER_EGNI : BinaryOpNoRet<IL_OP_BARRIER, (outs),
33 (ins GPRI32:$flag, GPRI32:$id),
34 "fence_threads_memory_lds_gds_gws",
35 [(int_AMDIL_barrier GPRI32:$flag, GPRI32:$id)]>;
36 }
37 let Predicates=[noRegionAS] in {
38 def BARRIER_7XX : BinaryOpNoRet<IL_OP_BARRIER, (outs),
39 (ins GPRI32:$flag, GPRI32:$id),
40 "fence_threads_memory_lds",
41 [(int_AMDIL_barrier GPRI32:$flag, GPRI32:$id)]>;
42 }
43
44 def BARRIER_LOCAL : BinaryOpNoRet<IL_OP_BARRIER_LOCAL, (outs),
45 (ins GPRI32:$flag, GPRI32:$id),
46 "fence_threads_lds",
47 [(int_AMDIL_barrier_local GPRI32:$flag, GPRI32:$id)]>;
48
49 def BARRIER_GLOBAL : BinaryOpNoRet<IL_OP_BARRIER_GLOBAL, (outs),
50 (ins GPRI32:$flag, GPRI32:$id),
51 "fence_threads_memory",
52 [(int_AMDIL_barrier_global GPRI32:$flag, GPRI32:$id)]>;
53
54 def BARRIER_REGION : BinaryOpNoRet<IL_OP_BARRIER_REGION, (outs),
55 (ins GPRI32:$flag, GPRI32:$id),
56 "fence_threads_gds",
57 [(int_AMDIL_barrier_region GPRI32:$flag, GPRI32:$id)]>;
58 }