6 SIRegisterGetHWRegNum.inc \
7 AMDILGenRegisterInfo.inc \
8 AMDILGenInstrInfo.inc \
9 AMDILGenAsmWriter.inc \
11 AMDILGenCallingConv.inc \
12 AMDILGenSubtargetInfo.inc \
14 AMDILGenIntrinsics.inc \
15 AMDILGenCodeEmitter.inc
19 AMDILCFGStructurizer.cpp \
22 AMDILEvergreenDevice.cpp \
23 AMDILFrameLowering.cpp \
25 AMDILIntrinsicInfo.cpp \
26 AMDILISelDAGToDAG.cpp \
27 AMDILISelLowering.cpp \
29 AMDILPeepholeOptimizer.cpp \
30 AMDILRegisterInfo.cpp \
33 AMDGPUTargetMachine.cpp \
34 AMDGPUISelLowering.cpp \
35 AMDGPUConvertToISA.cpp \
36 AMDGPULowerInstructions.cpp \
38 AMDGPURegisterInfo.cpp \
41 R600ISelLowering.cpp \
43 R600KernelParameters.cpp \
44 R600LowerInstructions.cpp \
45 R600MachineFunctionInfo.cpp \
46 R600RegisterInfo.cpp \
47 SIAssignInterpRegs.cpp \
51 SIMachineFunctionInfo.cpp \
52 SIPropagateImmReads.cpp \
54 MCTargetDesc/AMDILMCAsmInfo.cpp \
55 MCTargetDesc/AMDILMCTargetDesc.cpp \
56 TargetInfo/AMDILTargetInfo.cpp \
60 radeon_setup_tgsi_llvm.c