3 R600ShaderPatterns.td \
7 SIRegisterGetHWRegNum.inc \
8 AMDILGenRegisterInfo.inc \
9 AMDILGenInstrInfo.inc \
10 AMDILGenAsmWriter.inc \
12 AMDILGenCallingConv.inc \
13 AMDILGenSubtargetInfo.inc \
15 AMDILGenIntrinsics.inc \
16 AMDILGenCodeEmitter.inc \
17 AMDGPUInstrEnums.h.include \
18 AMDGPUInstrEnums.include
23 AMDILBarrierDetect.cpp \
24 AMDILCFGStructurizer.cpp \
27 AMDILEvergreenDevice.cpp \
28 AMDILELFWriterInfo.cpp \
29 AMDILFrameLowering.cpp \
30 AMDILGlobalManager.cpp \
33 AMDILIntrinsicInfo.cpp \
34 AMDILISelDAGToDAG.cpp \
35 AMDILISelLowering.cpp \
36 AMDILKernelManager.cpp \
37 AMDILLiteralManager.cpp \
38 AMDILMachineFunctionInfo.cpp \
39 AMDILMachinePeephole.cpp \
40 AMDILMCCodeEmitter.cpp \
43 AMDILPeepholeOptimizer.cpp \
44 AMDILPrintfConvert.cpp \
45 AMDILRegisterInfo.cpp \
48 AMDILTargetMachine.cpp \
49 AMDILUtilityFunctions.cpp \
50 AMDGPUTargetMachine.cpp \
51 AMDGPUISelLowering.cpp \
52 AMDGPUConvertToISA.cpp \
53 AMDGPULowerInstructions.cpp \
54 AMDGPULowerShaderInstructions.cpp \
55 AMDGPUReorderPreloadInstructions.cpp \
57 AMDGPURegisterInfo.cpp \
60 R600ISelLowering.cpp \
62 R600KernelParameters.cpp \
63 R600LowerInstructions.cpp \
64 R600LowerShaderInstructions.cpp \
65 R600RegisterInfo.cpp \
66 SIAssignInterpRegs.cpp \
70 SILowerShaderInstructions.cpp \
71 SIMachineFunctionInfo.cpp \
72 SIPropagateImmReads.cpp \
74 MCTargetDesc/AMDILMCAsmInfo.cpp \
75 MCTargetDesc/AMDILMCTargetDesc.cpp \
76 TargetInfo/AMDILTargetInfo.cpp \
80 radeon_setup_tgsi_llvm.c