7 SIRegisterGetHWRegNum.inc \
8 AMDILGenRegisterInfo.inc \
9 AMDILGenInstrInfo.inc \
10 AMDILGenAsmWriter.inc \
12 AMDILGenCallingConv.inc \
13 AMDILGenSubtargetInfo.inc \
15 AMDILGenIntrinsics.inc \
16 AMDILGenCodeEmitter.inc \
17 AMDGPUInstrEnums.h.include \
18 AMDGPUInstrEnums.include
22 AMDILCFGStructurizer.cpp \
25 AMDILEvergreenDevice.cpp \
26 AMDILFrameLowering.cpp \
28 AMDILIntrinsicInfo.cpp \
29 AMDILISelDAGToDAG.cpp \
30 AMDILISelLowering.cpp \
31 AMDILMachinePeephole.cpp \
33 AMDILPeepholeOptimizer.cpp \
34 AMDILRegisterInfo.cpp \
37 AMDILTargetMachine.cpp \
38 AMDGPUTargetMachine.cpp \
39 AMDGPUISelLowering.cpp \
40 AMDGPUConvertToISA.cpp \
41 AMDGPULowerInstructions.cpp \
43 AMDGPURegisterInfo.cpp \
46 R600ISelLowering.cpp \
48 R600KernelParameters.cpp \
49 R600LowerInstructions.cpp \
50 R600MachineFunctionInfo.cpp \
51 R600RegisterInfo.cpp \
52 SIAssignInterpRegs.cpp \
56 SIMachineFunctionInfo.cpp \
57 SIPropagateImmReads.cpp \
59 MCTargetDesc/AMDILMCAsmInfo.cpp \
60 MCTargetDesc/AMDILMCTargetDesc.cpp \
61 TargetInfo/AMDILTargetInfo.cpp \
65 radeon_setup_tgsi_llvm.c