9e3b6b5958b91c1ab4a741521989fc4783e380c4
1 //===-- R600ISelLowering.cpp - TODO: Add brief description -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TODO: Add full description
12 //===----------------------------------------------------------------------===//
14 #include "R600ISelLowering.h"
15 #include "R600InstrInfo.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 R600TargetLowering::R600TargetLowering(TargetMachine
&TM
) :
21 AMDGPUTargetLowering(TM
),
22 TII(static_cast<const R600InstrInfo
*>(TM
.getInstrInfo()))
24 setOperationAction(ISD::MUL
, MVT::i64
, Expand
);
25 // setSchedulingPreference(Sched::VLIW);
26 addRegisterClass(MVT::v4f32
, &AMDIL::R600_Reg128RegClass
);
27 addRegisterClass(MVT::f32
, &AMDIL::R600_Reg32RegClass
);
28 addRegisterClass(MVT::v4i32
, &AMDIL::R600_Reg128RegClass
);
29 addRegisterClass(MVT::i32
, &AMDIL::R600_Reg32RegClass
);
31 setOperationAction(ISD::EXTRACT_VECTOR_ELT
, MVT::v4f32
, Legal
);
32 setOperationAction(ISD::INSERT_VECTOR_ELT
, MVT::v4f32
, Legal
);
33 setOperationAction(ISD::EXTRACT_VECTOR_ELT
, MVT::v4i32
, Legal
);
34 setOperationAction(ISD::INSERT_VECTOR_ELT
, MVT::v4i32
, Legal
);
37 MachineBasicBlock
* R600TargetLowering::EmitInstrWithCustomInserter(
38 MachineInstr
* MI
, MachineBasicBlock
* BB
) const
40 MachineFunction
* MF
= BB
->getParent();
41 MachineRegisterInfo
&MRI
= MF
->getRegInfo();
43 switch (MI
->getOpcode()) {
44 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI
, BB
);
45 /* XXX: Use helper function from AMDGPULowerShaderInstructions here */
47 addLiveIn(MI
, MF
, MRI
, TII
, AMDIL::T1_X
);
50 addLiveIn(MI
, MF
, MRI
, TII
, AMDIL::T1_Y
);
53 addLiveIn(MI
, MF
, MRI
, TII
, AMDIL::T1_Z
);
56 addLiveIn(MI
, MF
, MRI
, TII
, AMDIL::T0_X
);
59 addLiveIn(MI
, MF
, MRI
, TII
, AMDIL::T0_Y
);
62 addLiveIn(MI
, MF
, MRI
, TII
, AMDIL::T0_Z
);
64 case AMDIL::NGROUPS_X
:
65 lowerImplicitParameter(MI
, *BB
, MRI
, 0);
67 case AMDIL::NGROUPS_Y
:
68 lowerImplicitParameter(MI
, *BB
, MRI
, 1);
70 case AMDIL::NGROUPS_Z
:
71 lowerImplicitParameter(MI
, *BB
, MRI
, 2);
73 case AMDIL::GLOBAL_SIZE_X
:
74 lowerImplicitParameter(MI
, *BB
, MRI
, 3);
76 case AMDIL::GLOBAL_SIZE_Y
:
77 lowerImplicitParameter(MI
, *BB
, MRI
, 4);
79 case AMDIL::GLOBAL_SIZE_Z
:
80 lowerImplicitParameter(MI
, *BB
, MRI
, 5);
82 case AMDIL::LOCAL_SIZE_X
:
83 lowerImplicitParameter(MI
, *BB
, MRI
, 6);
85 case AMDIL::LOCAL_SIZE_Y
:
86 lowerImplicitParameter(MI
, *BB
, MRI
, 7);
88 case AMDIL::LOCAL_SIZE_Z
:
89 lowerImplicitParameter(MI
, *BB
, MRI
, 8);
92 MI
->eraseFromParent();
96 void R600TargetLowering::lowerImplicitParameter(MachineInstr
*MI
, MachineBasicBlock
&BB
,
97 MachineRegisterInfo
& MRI
, unsigned dword_offset
) const
99 MachineBasicBlock::iterator I
= *MI
;
100 unsigned offsetReg
= MRI
.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass
);
101 MRI
.setRegClass(MI
->getOperand(0).getReg(), &AMDIL::R600_TReg32_XRegClass
);
103 BuildMI(BB
, I
, BB
.findDebugLoc(I
), TII
->get(AMDIL::MOV
), offsetReg
)
104 .addReg(AMDIL::ALU_LITERAL_X
)
105 .addImm(dword_offset
* 4);
107 BuildMI(BB
, I
, BB
.findDebugLoc(I
), TII
->get(AMDIL::VTX_READ_eg
))
108 .addOperand(MI
->getOperand(0))