src/gallium/drivers/radeon/R600ISelLowering.cpp

   1 //===-- R600ISelLowering.cpp - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "R600ISelLowering.h"
  15 #include "R600InstrInfo.h"
  16 #include "R600MachineFunctionInfo.h"
  17 #include "llvm/CodeGen/MachineRegisterInfo.h"
  18
  19 using namespace llvm;
  20
  21 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
  22     AMDGPUTargetLowering(TM),
  23     TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
  24 {
  25   setOperationAction(ISD::MUL, MVT::i64, Expand);
  26 //  setSchedulingPreference(Sched::VLIW);
  27   addRegisterClass(MVT::v4f32, &AMDIL::R600_Reg128RegClass);
  28   addRegisterClass(MVT::f32, &AMDIL::R600_Reg32RegClass);
  29   addRegisterClass(MVT::v4i32, &AMDIL::R600_Reg128RegClass);
  30   addRegisterClass(MVT::i32, &AMDIL::R600_Reg32RegClass);
  31
  32   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
  33   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
  34   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
  35   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
  36 }
  37
  38 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
  39     MachineInstr * MI, MachineBasicBlock * BB) const
  40 {
  41   MachineFunction * MF = BB->getParent();
  42   MachineRegisterInfo &MRI = MF->getRegInfo();
  43
  44   switch (MI->getOpcode()) {
  45   default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
  46   /* XXX: Use helper function from AMDGPULowerShaderInstructions here */
  47   case AMDIL::TGID_X:
  48     addLiveIn(MI, MF, MRI, TII, AMDIL::T1_X);
  49     break;
  50   case AMDIL::TGID_Y:
  51     addLiveIn(MI, MF, MRI, TII, AMDIL::T1_Y);
  52     break;
  53   case AMDIL::TGID_Z:
  54     addLiveIn(MI, MF, MRI, TII, AMDIL::T1_Z);
  55     break;
  56   case AMDIL::TIDIG_X:
  57     addLiveIn(MI, MF, MRI, TII, AMDIL::T0_X);
  58     break;
  59   case AMDIL::TIDIG_Y:
  60     addLiveIn(MI, MF, MRI, TII, AMDIL::T0_Y);
  61     break;
  62   case AMDIL::TIDIG_Z:
  63     addLiveIn(MI, MF, MRI, TII, AMDIL::T0_Z);
  64     break;
  65   case AMDIL::NGROUPS_X:
  66     lowerImplicitParameter(MI, *BB, MRI, 0);
  67     break;
  68   case AMDIL::NGROUPS_Y:
  69     lowerImplicitParameter(MI, *BB, MRI, 1);
  70     break;
  71   case AMDIL::NGROUPS_Z:
  72     lowerImplicitParameter(MI, *BB, MRI, 2);
  73     break;
  74   case AMDIL::GLOBAL_SIZE_X:
  75     lowerImplicitParameter(MI, *BB, MRI, 3);
  76     break;
  77   case AMDIL::GLOBAL_SIZE_Y:
  78     lowerImplicitParameter(MI, *BB, MRI, 4);
  79     break;
  80   case AMDIL::GLOBAL_SIZE_Z:
  81     lowerImplicitParameter(MI, *BB, MRI, 5);
  82     break;
  83   case AMDIL::LOCAL_SIZE_X:
  84     lowerImplicitParameter(MI, *BB, MRI, 6);
  85     break;
  86   case AMDIL::LOCAL_SIZE_Y:
  87     lowerImplicitParameter(MI, *BB, MRI, 7);
  88     break;
  89   case AMDIL::LOCAL_SIZE_Z:
  90     lowerImplicitParameter(MI, *BB, MRI, 8);
  91     break;
  92   case AMDIL::LOAD_INPUT:
  93     {
  94       int64_t RegIndex = MI->getOperand(1).getImm();
  95       addLiveIn(MI, MF, MRI, TII,
  96                 AMDIL::R600_TReg32RegClass.getRegister(RegIndex));
  97       MI->eraseFromParent();
  98       break;
  99     }
 100   case AMDIL::STORE_OUTPUT:
 101     {
 102       MachineBasicBlock::iterator I = *MI;
 103       int64_t OutputIndex = MI->getOperand(1).getImm();
 104       unsigned OutputReg = AMDIL::R600_TReg32RegClass.getRegister(OutputIndex);
 105
 106       BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::COPY), OutputReg)
 107                   .addOperand(MI->getOperand(0));
 108
 109       if (!MRI.isLiveOut(OutputReg)) {
 110         MRI.addLiveOut(OutputReg);
 111       }
 112       MI->eraseFromParent();
 113       break;
 114     }
 115
 116   case AMDIL::RESERVE_REG:
 117     {
 118       R600MachineFunctionInfo * MFI = MF->getInfo<R600MachineFunctionInfo>();
 119       int64_t ReservedIndex = MI->getOperand(0).getImm();
 120       unsigned ReservedReg =
 121                           AMDIL::R600_TReg32RegClass.getRegister(ReservedIndex);
 122       MFI->ReservedRegs.push_back(ReservedReg);
 123       MI->eraseFromParent();
 124       break;
 125     }
 126   }
 127
 128   return BB;
 129 }
 130
 131 void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
 132     MachineRegisterInfo & MRI, unsigned dword_offset) const
 133 {
 134   MachineBasicBlock::iterator I = *MI;
 135   unsigned offsetReg = MRI.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
 136   MRI.setRegClass(MI->getOperand(0).getReg(), &AMDIL::R600_TReg32_XRegClass);
 137
 138   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::MOV), offsetReg)
 139           .addReg(AMDIL::ALU_LITERAL_X)
 140           .addImm(dword_offset * 4);
 141
 142   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::VTX_READ_eg))
 143           .addOperand(MI->getOperand(0))
 144           .addReg(offsetReg)
 145           .addImm(0);
 146 }