src/gallium/drivers/radeon/R600InstrInfo.cpp

   1 //===-- R600InstrInfo.cpp - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "R600InstrInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16 #include "R600RegisterInfo.h"
  17
  18 using namespace llvm;
  19
  20 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
  21   : AMDGPUInstrInfo(tm),
  22     RI(tm, *this),
  23     TM(tm)
  24   { }
  25
  26 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const
  27 {
  28   return RI;
  29 }
  30
  31 bool R600InstrInfo::isTrig(const MachineInstr &MI) const
  32 {
  33   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
  34 }
  35
  36 void
  37 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  38                            MachineBasicBlock::iterator MI, DebugLoc DL,
  39                            unsigned DestReg, unsigned SrcReg,
  40                            bool KillSrc) const
  41 {
  42
  43   unsigned subRegMap[4] = {AMDIL::sel_x, AMDIL::sel_y, AMDIL::sel_z, AMDIL::sel_w};
  44
  45   if (AMDIL::R600_Reg128RegClass.contains(DestReg)
  46       && AMDIL::R600_Reg128RegClass.contains(SrcReg)) {
  47     for (unsigned i = 0; i < 4; i++) {
  48       BuildMI(MBB, MI, DL, get(AMDIL::MOV))
  49               .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
  50               .addReg(RI.getSubReg(SrcReg, subRegMap[i]))
  51               .addReg(DestReg, RegState::Define | RegState::Implicit);
  52     }
  53   } else {
  54
  55     /* We can't copy vec4 registers */
  56     assert(!AMDIL::R600_Reg128RegClass.contains(DestReg)
  57            && !AMDIL::R600_Reg128RegClass.contains(SrcReg));
  58
  59     BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
  60       .addReg(SrcReg, getKillRegState(KillSrc));
  61   }
  62 }
  63
  64 unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
  65 {
  66   switch (opcode) {
  67     default: return AMDGPUInstrInfo::getISAOpcode(opcode);
  68     case AMDIL::CUSTOM_ADD_i32:
  69       return AMDIL::ADD_INT;
  70     case AMDIL::CUSTOM_XOR_i32:
  71       return AMDIL::XOR_INT;
  72     case AMDIL::MOVE_f32:
  73     case AMDIL::MOVE_i32:
  74       return AMDIL::MOV;
  75     case AMDIL::SHR_i32:
  76       return getLSHRop();
  77   }
  78 }
  79
  80 unsigned R600InstrInfo::getLSHRop() const
  81 {
  82   unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
  83   if (gen < AMDILDeviceInfo::HD5XXX) {
  84     return AMDIL::LSHR_r600;
  85   } else {
  86     return AMDIL::LSHR_eg;
  87   }
  88 }
  89
  90 unsigned R600InstrInfo::getMULHI_UINT() const
  91 {
  92   unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
  93
  94   if (gen < AMDILDeviceInfo::HD5XXX) {
  95     return AMDIL::MULHI_UINT_r600;
  96   } else {
  97     return AMDIL::MULHI_UINT_eg;
  98   }
  99 }
 100
 101 unsigned R600InstrInfo::getMULLO_UINT() const
 102 {
 103   unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
 104
 105   if (gen < AMDILDeviceInfo::HD5XXX) {
 106     return AMDIL::MULLO_UINT_r600;
 107   } else {
 108     return AMDIL::MULLO_UINT_eg;
 109   }
 110 }
 111
 112 unsigned R600InstrInfo::getRECIP_UINT() const
 113 {
 114   const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
 115
 116   if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX) {
 117     return AMDIL::RECIP_UINT_r600;
 118   } else if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
 119     return AMDIL::RECIP_UINT_eg;
 120   } else {
 121     return AMDIL::RECIP_UINT_cm;
 122   }
 123 }